Searched +full:25 +full:mhz (Results 1 – 25 of 45) sorted by relevance
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| /Documentation/devicetree/bindings/net/ |
| D | adi,adin.yaml | 42 A 25MHz reference and a free-running 125MHz.
44 the 125MHz clocks based on its internal state.
47 - 25mhz-reference
48 - 125mhz-free-running
52 description: Enable 25MHz reference clock output on CLK25_REF pin.
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| D | micrel.txt | 23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
24 bit selects 25 MHz mode
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
27 than 50 MHz clock mode.
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| D | nxp,tja11xx.yaml | 54 typically derived from an external 25MHz crystal. Alternatively,
55 a 50MHz clock signal generated by an external oscillator can be
56 connected to pin REF_CLK. A third option is to connect a 25MHz
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| D | wiznet,w5x00.txt | 25 According to the w5500 datasheet, the chip allows a maximum of 80 MHz, however,
39 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
46 brcm,pins = <25>;
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| D | qca,qca7000.txt | 50 interrupts = <25 0x1>; /* Index: 25, rising edge */
53 spi-max-frequency = <8000000>; /* freq: 8 MHz */
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| D | stm32-dwmac.yaml | 94 set this property in RMII mode when you have PHY without crystal 50MHz and want to
106 set this property in RMII mode when you have PHY without crystal 50MHz and want to
189 clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>;
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| /Documentation/devicetree/bindings/clock/ |
| D | sophgo,sg2042-pll.yaml | 21 - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz)
22 - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz)
23 - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz)
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| D | starfive,jh7100-clkgen.yaml | 22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
24 - description: RMII reference clock (50 MHz)
25 - description: RGMII RX clock (125 MHz)
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| D | allwinner,sun7i-a20-gmac-clk.yaml | 26 The parent clocks shall be fixed rate dummy clocks at 25 MHz and
27 125 MHz, respectively.
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| D | pwm-clock.yaml | 43 pwms = <&pwm2 0 40>; /* 1 / 40 ns = 25 MHz */
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| D | zynq-7000.txt | 7 See Chapter 25 of Zynq TRM for more information about Zynq clocks.
19 (usually 33 MHz oscillators are used for Zynq platforms)
66 25: spi0
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| D | idt,versaclock5.yaml | 157 /* 25MHz reference crystal */
175 /* Connect XIN input to 25MHz reference */
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| D | arm,syscon-icst.yaml | 31 from a 24 MHz clock on the motherboard (usually the main crystal) used for
43 Integrator/AP 22 or 1 17 or (33 or 25 MHz)
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| D | st,stm32mp25-rcc.yaml | 36 - description: CK_SCMI_HSE High Speed External oscillator (8 to 48 MHz)
37 - description: CK_SCMI_HSI High Speed Internal oscillator (~ 64 MHz)
38 - description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz)
68 - description: CK_SCMI_FLEXGEN_25 flexgen clock 25
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| D | amlogic,s4-peripherals-clkc.yaml | 36 - description: input oscillator (usually at 24MHz)
85 <&clkc_pll 25>,
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| D | st,nomadik.txt | 18 i.e. the driver output for the main (~19.2 MHz) chrystal,
69 25: PCLKHSEM
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| D | renesas,9series.yaml | 88 /* 25MHz reference crystal */
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| /Documentation/fb/ |
| D | viafb.modes | 10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
49 # 25 chars 20 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
66 # 10 chars 25 lines
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
75 geometry 640 480 640 480 32 timings 27777 80 56 25 1 56 3 endmode
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| /Documentation/devicetree/bindings/mmc/ |
| D | davinci_mmc.txt | 15 - max-frequency: Maximum operating clock frequency, default 25MHz.
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| /Documentation/devicetree/bindings/watchdog/ |
| D | marvel.txt | 30 "fixed" (Reference 25 MHz fixed-clock).
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| /Documentation/admin-guide/media/ |
| D | dvb_intro.rst | 17 video) is an analogue encoding of a sequence of image frames (25 frames
38 signal encoded at a resolution of 768x576 24-bit color pixels over 25
107 Seven 177.500 Mhz
108 SBS 184.500 Mhz
109 Nine 191.625 Mhz
110 Ten 219.500 Mhz
111 ABC 226.500 Mhz
112 Channel 31 557.625 Mhz
133 T 177500000 7MHz AUTO AUTO QAM64 8k 1/16 NONE
134 T 184500000 7MHz AUTO AUTO QAM64 8k 1/8 NONE
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| /Documentation/devicetree/bindings/timer/ |
| D | marvell,armada-370-xp-timer.txt | 23 "fixed" (Reference 25 MHz fixed-clock).
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| /Documentation/scsi/ |
| D | 53c700.rst | 61 53c700 25MHz
62 53c700-66 50MHz
63 53c710 40Mhz
106 Set to the clock speed of the chip in MHz.
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | microchip,ksz.yaml | 48 Set if the output SYNCLKO frequency should be set to 125MHz instead of 25MHz.
140 cs-gpios = <&pioC 25 0>;
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| /Documentation/userspace-api/media/v4l/ |
| D | vidioc-enumstd.rst | 137 rate, and PAL color modulation with a 4.43 MHz color subcarrier. Some
148 rate, and NTSC color modulation with a 4.43 MHz color subcarrier.
256 - :cspan:`8` 1/25
268 * - Nominal radio-frequency channel bandwidth (MHz)
280 * - Sound carrier relative to vision carrier (MHz)
331 New Zealand uses a sound carrier displaced 5.4996 ± 0.0005 MHz from
337 is being introduced. The second carrier is 5.85 MHz above the vision
343 second sound carrier is 6.552 MHz above the vision carrier and is
348 In France, a digital carrier 5.85 MHz away from the vision carrier
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