Home
last modified time | relevance | path

Searched +full:25 +full:v (Results 1 – 25 of 70) sorted by relevance

123

/Documentation/devicetree/bindings/pci/
Dmediatek,mt7621-pcie.yaml26 v
31 v v v On Bus0
39 On Bus1 v On Bus2 v On Bus3 v
129 <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
155 resets = <&rstctrl 25>;
156 clocks = <&clkctrl 25>;
169 interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
/Documentation/fb/
Dviafb.modes29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
49 # 25 chars 20 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
66 # 10 chars 25 lines
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
75 geometry 640 480 640 480 32 timings 27777 80 56 25 1 56 3 endmode
87 # 13 chars 25 lines
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
96 geometry 640 480 640 480 32 timings 23168 104 40 25 1 64 3 endmode
[all …]
/Documentation/devicetree/bindings/iio/adc/
Dadi,ad7091r5.yaml33 Provide VDD power to the sensor (VDD range is from 2.7V to 5.25V).
38 The V_drive voltage range is from 1.8V to 5.25V and must not exceed VDD by
39 more than 0.3V.
106 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
122 convst-gpios = <&gpio 25 GPIO_ACTIVE_LOW>;
Dadi,ad7606.yaml89 is tied to a logic high, the analog input range is ±10V for all channels.
91 is ±5V for all channels. As the line is active high, it should be marked
193 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
/Documentation/devicetree/bindings/leds/backlight/
Drichtek,rt4831-backlight.yaml44 Backlight OVP level selection, currently support 17V/21V/25V/29V.
Dqcom-wled.yaml67 maximum: 25
72 default: 25
75 multipleOf: 25
91 V; Over-voltage protection limit.
/Documentation/devicetree/bindings/sound/
Dadi,adau1701.txt23 - avdd-supply: Power supply for AVDD, providing 3.3V
24 - dvdd-supply: Power supply for DVDD, providing 3.3V
35 adi,pll-mode-gpios = <&gpio 24 0 &gpio 25 0>;
Drichtek,rtq9128.yaml15 THD+N from a 25V supply in automotive applications.
/Documentation/devicetree/bindings/display/panel/
Dsony,tulip-truly-nt35521.yaml28 description: Positive 5V supply
31 description: Negative 5V supply
63 reset-gpios = <&msmgpio 25 GPIO_ACTIVE_LOW>;
/Documentation/devicetree/bindings/media/i2c/
Dsony,imx214.yaml14 an active array size of 4224H x 3200V. It is programmable through an I2C
42 description: Chip digital IO regulator (1.8V).
45 description: Chip analog regulator (2.7V).
48 description: Chip digital core regulator (1.12V).
111 enable-gpios = <&msmgpio 25 GPIO_ACTIVE_HIGH>;
/Documentation/userspace-api/media/dvb/
Dca_high_level.rst106 (25) ES type=[4] ES pid=[301] ES length =[0 (0x0)]
107 ca_message length is 25 (0x19) bytes
136 v
141 | v |
145 | v |
149 | v |
154 v
/Documentation/devicetree/bindings/hwmon/
Dmaxim,max20730.yaml16 with PMBus for applications operating from 4.5V to 16V and requiring
17 up to 25A (max) load. This single-chip regulator provides extremely
/Documentation/spi/
Dspi-lm70llp.rst40 D1 3 --> V+ 5
41 D2 4 --> V+ 5
42 D3 5 --> V+ 5
43 D4 6 --> V+ 5
47 GND 25 - GND 7
/Documentation/hwmon/
Df71805f.rst68 range is thus from 0 to 2.040 V. Voltage values outside of this range
70 the chip's own power source (+3.3V), and is divided internally by a
83 in0 VCC VCC3.3V int. int. 2.00 1.65 V
84 in1 VIN1 VTT1.2V 10K - 1.00 1.20 V
85 in2 VIN2 VRAM 100K 100K 2.00 ~1.25 V [1]_
86 in3 VIN3 VCHIPSET 47K 100K 1.47 2.24 V [2]_
87 in4 VIN4 VCC5V 200K 47K 5.25 0.95 V
88 in5 VIN5 +12V 200K 20K 11.00 1.05 V
89 in6 VIN6 VCC1.5V 10K - 1.00 1.50 V
90 in7 VIN7 VCORE 10K - 1.00 ~1.40 V [1]_
[all …]
Dvt1211.rst71 UCH2 in1 temp4 +2.5V
73 UCH4 in3 temp6 +5V
74 UCH5 in4 temp7 +12V
75 +3.3V in5 Internal VCC (+3.3V)
83 range is thus from 0 to 2.60V. Voltage values outside of this range need
98 +2.5V 2K 10K 1.2 2083 mV
100 +5V 14K 10K 2.4 2083 mV
101 +12V 47K 10K 5.7 2105 mV
102 +3.3V (int) 2K 3.4K 1.588 3300 mV [2]_
103 +3.3V (ext) 6.8K 10K 1.68 1964 mV
[all …]
/Documentation/devicetree/bindings/mfd/
Dmaxim,max14577.yaml106 pmic@25 {
149 pmic@25 {
175 regulator-name = "MOT_2.7V";
/Documentation/isdn/
Dcredits.rst16 For X.25 implementation.
60 For V.110, extended T.70 and Hylafax extensions in isdn_tty.c
/Documentation/translations/zh_CN/power/
Denergy-model.rst47 v v v
133 Power = C * V^2 * f
194 25 struct em_data_callback em_cb = EM_DATA_CB(est_power);
/Documentation/devicetree/bindings/clock/
Drenesas,9series.yaml74 description: Output clock slew rate select in V/ns
88 /* 25MHz reference crystal */
/Documentation/ABI/testing/
Dsysfs-driver-zynqmp-fpga9 https://docs.xilinx.com/v/u/en-US/ug570-ultrascale-configuration
66 BIT(25) to BIT(26) Indicates the detected bus width
/Documentation/admin-guide/auxdisplay/
Dcfag12864b.rst64 (10) [+5v]---( 1) Vdd
66 (12) [+5v]---(14) Reset
72 Ground (18)---[GND] [+5v]---(19) LED +
79 Ground (25)---[GND] [GND]---[P2]---[R]---(20) LED -
/Documentation/userspace-api/media/v4l/
Dselection.svg54 …<path d="M352.25 211.99c-3.804-25.264-16.81-50.638-17.157-75.525-.186-13.356 3.273-26.571 13.756-3…
57 …<path d="M352.25 211.99c-3.804-25.264-16.81-50.638-17.157-75.525-.186-13.356 3.273-26.571 13.756-3…
60 …<path d="M352.25 211.99c-3.804-25.264-16.81-50.638-17.157-75.525-.186-13.356 3.273-26.571 13.756-3…
63 …<path d="M352.25 211.99c-3.804-25.264-16.81-50.638-17.157-75.525-.186-13.356 3.273-26.571 13.756-3…
108 …<path d="M352.25 211.99c-3.804-25.264-16.81-50.638-17.157-75.525-.186-13.356 3.273-26.571 13.756-3…
306 …-1.76-.163-5.531.25-3.542.39-9.008 1.21-10.281 1.876-1.6-.295-3.887-.507-5.875-.313-3.059.3-4.941.…
307 …3.86-.42-5.843-.188-3.052.358-4.945.568-6.875.781-.657.073-1.041.173-1.344.25-.427.128-.685.268-1.…
308 …498-5.5 1.218a1047.26 1047.26 0 0 1-6.437 2.469c-.617.233-.997.442-1.281.594v.03l-8 3.188 1.812 14…
309 …25c1.133-.23 2.304.209 6.343-.5 4.04-.709 5.5-.927 6.22-1.187.715-.26 1.704-.568 2.343-1.094 1.924…
310 …56 2.266-.63 3.032-.874.24-.088.463-.122.75-.156 1.148-.14 2.316.34 6.375-.25 4.058-.59 5.562-.778…
[all …]
Dsubdev-formats.rst240 - 25
1904 - 25
2124 - 25
3290 and V components. Some formats include dummy bits in some of their
3297 - The Y, U and V components order code, as transferred on the bus.
3319 the U, Y, V, Y order will be named ``MEDIA_BUS_FMT_UYVY8_2X8``.
3333 - v\ :sub:`x` for red chroma component bit number x
3374 - 25
3501 - v\ :sub:`7`
3502 - v\ :sub:`6`
[all …]
/Documentation/devicetree/bindings/mmc/
Dmmc-controller.yaml124 no-1-8-v:
127 When specified, denotes that 1.8V card voltage is not supported
193 eMMC high-speed DDR mode (1.2V I/O) is supported.
198 eMMC high-speed DDR mode (1.8V I/O) is supported.
203 eMMC high-speed DDR mode (3.3V I/O) is supported.
208 eMMC HS200 mode (1.2V I/O) is supported.
213 eMMC HS200 mode (1.8V I/O) is supported.
218 eMMC HS400 mode (1.2V I/O) is supported.
223 eMMC HS400 mode (1.8V I/O) is supported.
348 "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
/Documentation/admin-guide/media/
Dcec.rst69 frequency change to 1/25th, which keeps the CEC timings within spec.
328 If you want to monitor the HPD and/or 5V lines as well, then you need one of
329 these 5V to 3.3V level shifters:
342 The optional 5V pin of the HDMI connector should be connected via the
343 level shifter to these pins: GPIO 25 and GPIO 22. Monitoring the HPD and
344 5V lines is not necessary, but it is helpful.
353 v5-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
363 If you haven't hooked up the HPD and/or 5V lines, then just delete those

123