| /Documentation/userspace-api/media/dvb/ |
| D | fe-bandwidth-t.rst | 20 - .. row 2
30 - .. _BANDWIDTH-1-712-MHZ:
34 - 1.712 MHz
38 - .. _BANDWIDTH-5-MHZ:
42 - 5 MHz
46 - .. _BANDWIDTH-6-MHZ:
50 - 6 MHz
54 - .. _BANDWIDTH-7-MHZ:
58 - 7 MHz
62 - .. _BANDWIDTH-8-MHZ:
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| /Documentation/fb/ |
| D | viafb.modes | 10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
16 # 12 chars 2 lines
18 # 2 chars 10 lines
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
43 # 2 chars 1 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
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| /Documentation/devicetree/bindings/mfd/ |
| D | omap-usb-host.txt | 29 "ohci-tll-2pin-datse0",
30 "ohci-tll-2pin-dpdm",
40 * "usbhost_120m_fck" - 120MHz Functional clock.
43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
47 * "utmi_p2_gfclk" - Port 2 UTMI clock mux.
49 * "usb_host_hs_utmi_p2_clk" - Port 2 UTMI clock gate.
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
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| /Documentation/devicetree/bindings/cpu/ |
| D | cpu-capacity.txt | 15 2 - CPU capacity definition
38 by the frequency (in MHz) at which the benchmark has been run, so that
39 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
55 mhz values (normalized w.r.t. the highest value found while parsing the DT).
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
69 #address-cells = <2>;
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| /Documentation/devicetree/bindings/clock/ |
| D | armada3700-periph-clock.txt | 17 2 sec_at Security AT
24 9 i2c_2 I2C 2
36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
47 11 usb32-sub2-sys USB 2 clock
68 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
|
| D | maxim,max9485.txt | 5 - MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
8 - MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT
10 MAX9485_CLKOUT[1,2] are children of MAX9485_CLKOUT which upchain all rate set
15 - clocks: Input clock, must provide 27.000 MHz
34 xo-27mhz: xo-27mhz {
45 clocks = <&xo-27mhz>;
|
| D | starfive,jh7100-clkgen.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
24 - description: RMII reference clock (50 MHz)
25 - description: RGMII RX clock (125 MHz)
|
| D | samsung,exynos850-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
20 two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
73 - description: External reference clock (26 MHz)
89 - description: External reference clock (26 MHz)
107 - description: External reference clock (26 MHz)
125 - description: External reference clock (26 MHz)
143 - description: External reference clock (26 MHz)
167 - description: External reference clock (26 MHz)
187 - description: External reference clock (26 MHz)
207 - description: External reference clock (26 MHz)
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| D | samsung,exynosautov9-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
20 two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz).
71 - description: External reference clock (26 MHz)
87 - description: External reference clock (26 MHz)
105 - description: External reference clock (26 MHz)
123 - description: External reference clock (26 MHz)
141 - description: External reference clock (26 MHz)
161 - description: External reference clock (26 MHz)
183 - description: External reference clock (26 MHz)
205 - description: External reference clock (26 MHz)
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| D | tesla,fsd-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
16 The root clock comes from external OSC clock (24 MHz).
56 - description: External reference clock (24 MHz)
70 - description: External reference clock (24 MHz)
90 - description: External reference clock (24 MHz)
114 - description: External reference clock (24 MHz)
134 - description: External reference clock (24 MHz)
152 - description: External reference clock (24 MHz)
166 - description: External reference clock (24 MHz)
|
| D | sophgo,sg2042-pll.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
21 - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz)
22 - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz)
23 - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz)
|
| D | samsung,exynosautov920-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
19 two external clocks:: OSCCLK/XTCXO (38.4 MHz) and RTCCLK/XrtcXTI (32768 Hz).
66 - description: External reference clock (38.4 MHz)
84 - description: External reference clock (38.4 MHz)
105 - description: External reference clock (38.4 MHz)
123 - description: External reference clock (38.4 MHz)
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | sony,imx415.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
18 available via CSI-2 serial data output (two or four lanes).
31 description: Input clock (24 MHz, 27 MHz, 37.125 MHz, 72 MHz or 74.25 MHz)
61 - const: 2
64 - const: 2
101 orientation = <2>;
108 data-lanes = <1 2 3 4>;
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| D | sony,imx412.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
18 sent through MIPI CSI-2.
34 description: Clock frequency 6MHz, 12MHz, 18MHz, 24MHz or 27MHz
96 data-lanes = <1 2 3 4>;
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| D | sony,imx334.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
18 sent through MIPI CSI-2.
32 description: Clock frequency from 6 to 27 MHz, 37.125MHz, 74.25MHz
84 data-lanes = <1 2 3 4>;
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| /Documentation/admin-guide/pm/ |
| D | intel-speed-select.rst | 152 enable-cpu-list:0,1,2,3,4,5,6,7,8,9,10,11,12,13,28,29,30,31,32,33,34,35,36,37,38,39,40,41
154 base-frequency(MHz):2600
168 condition is met, then base frequency of 2600 MHz can be maintained. To
181 enable-cpu-list:0,1,2,3,5,7,8,9,10,11,28,29,30,31,33,35,36,37,38,39
183 base-frequency(MHz):2800
211 This matches the base-frequency (MHz) field value displayed from the
232 0 2 2 2600
261 Which shows that the base frequency now increased from 2600 MHz at performance
262 level 0 to 2800 MHz at performance level 4. As a result, any workload, which can
263 use fewer CPUs, can see a boost of 200 MHz compared to performance level 0.
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| /Documentation/scsi/ |
| D | dc395x.rst | 34 shortcut for dc395x=7,4,9,15,2,10
45 0 20 Mhz
46 1 12.2 Mhz
47 2 10 Mhz
48 3 8 Mhz
49 4 6.7 Mhz
51 6 5 Mhz
52 7 4 Mhz
64 1 0x02 2 Synchronous Negotiation
65 2 0x04 4 Disconnection
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| D | aic7xxx.rst | 13 2. Version History
26 aic7770 10 EISA/VL 10MHz 16Bit 4 1
27 aic7850 10 PCI/32 10MHz 8Bit 3
28 aic7855 10 PCI/32 10MHz 8Bit 3
29 aic7856 10 PCI/32 10MHz 8Bit 3
30 aic7859 10 PCI/32 20MHz 8Bit 3
31 aic7860 10 PCI/32 20MHz 8Bit 3
32 aic7870 10 PCI/32 10MHz 16Bit 16
33 aic7880 10 PCI/32 20MHz 16Bit 16
34 aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8
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| /Documentation/devicetree/bindings/mips/cavium/ |
| D | uctl.txt | 10 - #address-cells: Must be <2>.
12 - #size-cells: Must be <2>.
27 #address-cells = <2>;
28 #size-cells = <2>;
29 /* 12MHz, 24MHz and 48MHz allowed */
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| /Documentation/devicetree/bindings/net/ |
| D | qcom,ipq4019-mdio.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
34 maxItems: 2
42 - description: MDIO clock source frequency fixed to 100MHZ
53 MDC rate is feed by an external clock (fixed 100MHz) and is divider
57 To follow 802.3 standard that instruct up to 2.5MHz by default, if
59 default 1.5625Mhz is select.
108 ethphy2: ethernet-phy@2 {
109 reg = <2>;
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| /Documentation/devicetree/bindings/regulator/ |
| D | maxim,max8952.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
21 enum: [0, 1, 2, 3]
42 enum: [0, 1, 2, 3, 4, 5, 6, 7]
48 - 2: 8mV/us
50 - 4: 2mV/us
58 enum: [0, 1, 2]
62 - 0: 26 MHz
63 - 1: 13 MHz
64 - 2: 19.2 MHz
65 Defaults to 26 MHz if not specified.
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| D | mps,mpq7920.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
14 pattern: "pmic@[0-9a-f]{1,2}"
27 after their hardware counterparts BUCK[1-4], one LDORTC, and LDO[2-5]
32 enum: [0, 1, 2, 3]
33 default: 2
36 1.1MHz, 1.65MHz, 2.2MHz, 2.75MHz
56 enum: [0, 1, 2, 3]
63 enum: [0, 1, 2, 3]
105 mps,buck-phase-delay = /bits/ 8 <2>;
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| /Documentation/devicetree/bindings/usb/ |
| D | rockchip,rk3399-dwc3.yaml | 17 const: 2
20 const: 2
27 Controller reference clock, must to be 24 MHz
29 Controller suspend clock, must to be 24 MHz or 32 KHz
31 Master/Core clock, must to be >= 62.5 MHz for SS
32 operation and >= 30MHz for HS operation
78 #address-cells = <2>;
79 #size-cells = <2>;
83 #address-cells = <2>;
84 #size-cells = <2>;
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| D | rockchip,dwc3.yaml | 53 Controller reference clock, must to be 24 MHz
55 Controller suspend clock, must to be 24 MHz or 32 KHz
57 Master/Core clock, must to be >= 62.5 MHz for SS
58 operation and >= 30MHz for HS operation
145 #address-cells = <2>;
146 #size-cells = <2>;
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| /Documentation/admin-guide/media/ |
| D | dvb_intro.rst | 107 Seven 177.500 Mhz
108 SBS 184.500 Mhz
109 Nine 191.625 Mhz
110 Ten 219.500 Mhz
111 ABC 226.500 Mhz
112 Channel 31 557.625 Mhz
133 T 177500000 7MHz AUTO AUTO QAM64 8k 1/16 NONE
134 T 184500000 7MHz AUTO AUTO QAM64 8k 1/8 NONE
135 T 191625000 7MHz AUTO AUTO QAM64 8k 1/16 NONE
136 T 219500000 7MHz AUTO AUTO QAM64 8k 1/16 NONE
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