| /Documentation/hwmon/ |
| D | mc13783-adc.rst | 47 0 Battery Voltage (BATT) 2.50 - 4.65V -2.40V
49 2 Application Supply (BP) 2.50 - 4.65V -2.40V
50 3 Charger Voltage (CHRGRAW) 0 - 10V / /5
51 0 - 20V /10
52 4 Charger Current (CHRGISNSP-CHRGISNSN) -0.25 - 0.25V x4
53 5 General Purpose ADIN5 / Battery Pack Thermistor 0 - 2.30V No
54 6 General Purpose ADIN6 / Backup Voltage (LICELL) 0 - 2.30V / No /
55 1.50 - 3.50V -1.20V
56 7 General Purpose ADIN7 / UID / Die Temperature 0 - 2.30V / No /
57 0 - 2.55V / x0.9 / No
[all …]
|
| D | dme1737.rst | 64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and
69 For the DME1737, A8000 and SCH5027, fan[1-2] and pwm[1-2] are always present.
94 in0: +5VTR (+5V standby) 0V - 6.64V
95 in1: Vccp (processor core) 0V - 3V
96 in2: VCC (internal +3.3V) 0V - 4.38V
97 in3: +5V 0V - 6.64V
98 in4: +12V 0V - 16V
99 in5: VTR (+3.3V standby) 0V - 4.38V
100 in6: Vbat (+3.0V) 0V - 4.38V
104 in0: +2.5V 0V - 3.32V
[all …]
|
| D | ltc4245.rst | 49 rely on the sense resistors listed in Table 2: "Sense Resistor Values".
52 in1_input 12v input voltage (mV)
53 in2_input 5v input voltage (mV)
54 in3_input 3v input voltage (mV)
55 in4_input Vee (-12v) input voltage (mV)
57 in1_min_alarm 12v input undervoltage alarm
58 in2_min_alarm 5v input undervoltage alarm
59 in3_min_alarm 3v input undervoltage alarm
60 in4_min_alarm Vee (-12v) input undervoltage alarm
62 curr1_input 12v current (mA)
[all …]
|
| D | f71805f.rst | 68 range is thus from 0 to 2.040 V. Voltage values outside of this range
70 the chip's own power source (+3.3V), and is divided internally by a
71 factor 2. For the F71872F/FG, in9 (VSB) and in10 (battery) are also
72 divided internally by a factor 2.
83 in0 VCC VCC3.3V int. int. 2.00 1.65 V
84 in1 VIN1 VTT1.2V 10K - 1.00 1.20 V
85 in2 VIN2 VRAM 100K 100K 2.00 ~1.25 V [1]_
86 in3 VIN3 VCHIPSET 47K 100K 1.47 2.24 V [2]_
87 in4 VIN4 VCC5V 200K 47K 5.25 0.95 V
88 in5 VIN5 +12V 200K 20K 11.00 1.05 V
[all …]
|
| D | max197.rst | 25 The A/D converters MAX197, and MAX199 are both 8-Channel, Multi-Range, 5V,
28 The available ranges for the MAX197 are {0,-5V} to 5V, and {0,-10V} to 10V,
29 while they are {0,-2V} to 2V, and {0,-4V} to 4V on the MAX199.
51 2,1,0 A2,A1,A0 Channel
|
| D | smsc47m192.rst | 46 each voltage channel is 0V ... 255/192*(nominal voltage), the resolution
51 The +12V analog voltage input channel (in4_input) is multiplexed with
53 a +12V voltage measurement or a 5 bit CPU VID, but not both.
54 The default setting is to use the pin as 12V input, and use only 4 bit VID.
67 in0_input +2.5V voltage input
68 in1_input CPU voltage input (nominal 2.25V)
69 in2_input +3.3V voltage input
70 in3_input +5V voltage input
71 in4_input +12V voltage input (may be missing if used as VID4)
72 in5_input Vcc voltage input (nominal 3.3V)
[all …]
|
| /Documentation/userspace-api/media/v4l/ |
| D | subdev-formats.rst | 17 :widths: 1 1 2
184 1 and 2.
200 green and 5-bit blue values padded on the high bit, transferred as 2
220 \setlength{\tabcolsep}{2pt}
223 :header-rows: 2
225 :widths: 36 7 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
263 - 2
292 - r\ :sub:`2`
296 - g\ :sub:`2`
300 - b\ :sub:`2`
[all …]
|
| D | pixfmt-packed-hsv.rst | 14 The *saturation* (s) and the *value* (v) are measured in percentage of the
25 \setlength{\tabcolsep}{2pt}
32 :header-rows: 2
40 - :cspan:`7` Byte 2
50 - 2
59 - 2
68 - 2
77 - 2
99 - h\ :sub:`2`
108 - s\ :sub:`2`
[all …]
|
| /Documentation/devicetree/bindings/media/i2c/ |
| D | samsung,s5k5baf.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
7 title: Samsung S5K5BAF UXGA 1/5" 2M CMOS Image Sensor with embedded SoC ISP
39 description: Analog power supply 2.8V (2.6V to 3.0V)
42 description: I/O power supply 1.8V (1.65V to 1.95V) or 2.8V (2.5V to 3.1V)
46 Regulator input power supply 1.8V (1.7V to 1.9V) or 2.8V (2.6V to 3.0)
82 sensor@2d {
|
| D | thine,thp7312.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
17 MIPI CSI-2 and parallel interfaces. It can also output on either MIPI CSI-2
43 0 is for the SPI/2-wire slave boot, 1 is for the SPI master boot (from
54 1.2V supply for core, PLL, MIPI rx and MIPI tx.
58 Supply for input (RX). 1.8V for MIPI, or 1.8/2.8/3.3V for parallel.
62 Supply for output (TX). 1.8V for MIPI, or 1.8/2.8/3.3V for parallel.
66 Supply for host interface. 1.8V, 2.8V, or 3.3V.
70 Supply for sensor interface. 1.8V, 2.8V, or 3.3V.
74 Supply for GPIO_0. 1.8V, 2.8V, or 3.3V.
78 Supply for GPIO_1. 1.8V, 2.8V, or 3.3V.
[all …]
|
| D | sony,imx415.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
15 pixels. This chip operates with analog 2.9 V, digital 1.1 V, and interface
16 1.8 V triple power supply, and has low power consumption.
18 available via CSI-2 serial data output (two or four lanes).
35 description: Analog power supply (2.9 V)
38 description: Digital power supply (1.1 V)
41 description: Interface power supply (1.8 V)
61 - const: 2
64 - const: 2
101 orientation = <2>;
[all …]
|
| /Documentation/devicetree/bindings/sound/ |
| D | cs35l32.txt | 24 2 = (Default) Boost voltage fixed in Bypass Mode (VBST = VP).
25 3 = Boost voltage fixed at 5 V.
31 2 = (Default) left/right channels VMON[15:0], IMON [15:0].
40 0 = 3.1V
41 1 = 3.2V
42 2 = 3.3V (Default)
43 3 = 3.4V
46 0 = 3.1V
47 1 = 3.2V
48 2 = 3.3V
[all …]
|
| D | ti,ts3a227e.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
34 - 0 # 2.1 V
35 - 1 # 2.2 V
36 - 2 # 2.3 V
37 - 3 # 2.4 V
38 - 4 # 2.5 V
39 - 5 # 2.6 V
40 - 6 # 2.7 V
41 - 7 # 2.8 V
54 - 2
[all …]
|
| D | fsl,sgtl5000.yaml | 44 values of 2k, 4k or 8k. If set to 0 it will be off. If this node is not
47 enum: [ 0, 2, 4, 8 ]
51 values from 1.25V to 3V by 250mV steps. If this node is not mentioned
52 or the value is unknown, then the value is set to 1.25V.
58 The LRCLK pad strength. Possible values are: 0, 1, 2 and 3 as per the
61 VDDIO 1.8V 2.5V 3.3V
64 2 = 3.33 mA 5.74 mA 8.03 mA
67 enum: [ 0, 1, 2, 3 ]
71 The SCLK pad strength. Possible values are: 0, 1, 2 and 3 as per the
74 VDDIO 1.8V 2.5V 3.3V
[all …]
|
| D | wlf,wm8782.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
20 description: Regulator for the analog power supply (2.7V - 5.5V)
23 description: Regulator for the digital power supply (2.7V - 3.6V)
26 description: FSAMPEN pin value, 0 for low, 1 for high, 2 for disconnected.
28 enum: [0, 1, 2]
46 wlf,fsampen = <2>;
|
| /Documentation/devicetree/bindings/iio/dac/ |
| D | adi,ltc2664.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
14 Analog Devices LTC2664 4 channel, 12-/16-Bit, +-10V DAC
31 v-pos-supply:
34 v-neg-supply:
61 0 - MPS2=GND, MPS1=GND, MSP0=GND (+-10V, reset to 0V)
62 1 - MPS2=GND, MPS1=GND, MSP0=VCC (+-5V, reset to 0V)
63 2 - MPS2=GND, MPS1=VCC, MSP0=GND (+-2.5V, reset to 0V)
64 3 - MPS2=GND, MPS1=VCC, MSP0=VCC (0V to 10, reset to 0V)
65 4 - MPS2=VCC, MPS1=GND, MSP0=GND (0V to 10V, reset to 5V)
66 5 - MPS2=VCC, MPS1=GND, MSP0=VCC (0V to 5V, reset to 0V)
[all …]
|
| D | adi,ad3552r.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
46 internal reference will be used. External reference must be 2.5V
49 description: Vref I/O driven by internal vref to 2.5V. If not set, Vref pin
58 - 2: medium high SDO drive strength.
61 enum: [0, 1, 2, 3]
100 description: GainP = 1 / ( 2 ^ adi,gain-scaling-p)
102 enum: [0, 1, 2, 3]
105 description: GainN = 1 / ( 2 ^ adi,gain-scaling-n)
107 enum: [0, 1, 2, 3]
147 Rfb1x for: 0 to 2.5 V; 0 to 3V; 0 to 5 V;
[all …]
|
| /Documentation/virt/hyperv/ |
| D | overview.rst | 6 enlightened guest on Microsoft's Hyper-V hypervisor. Hyper-V
10 partitions. In this documentation, references to Hyper-V usually
15 Hyper-V runs on x86/x64 and arm64 architectures, and Linux guests
16 are supported on both. The functionality and behavior of Hyper-V is
19 Linux Guest Communication with Hyper-V
21 Linux guests communicate with Hyper-V in four different ways:
24 some guest actions trap to Hyper-V. Hyper-V emulates the action and
29 Hyper-V, passing parameters. Hyper-V performs the requested action
32 Hyper-V. On x86/x64, hypercalls use a Hyper-V specific calling
36 * Synthetic register access: Hyper-V implements a variety of
[all …]
|
| /Documentation/devicetree/bindings/regulator/ |
| D | ltc3589.txt | 1 Linear Technology LTC3589, LTC3589-1, and LTC3589-2 8-output regulators
4 - compatible: "lltc,ltc3589", "lltc,ltc3589-1" or "lltc,ltc3589-2"
21 0.3625 V to 0.75 V in 12.5 mV steps. The output voltage thus ranges between
22 0.3625 * (1 + R1/R2) V and 0.75 * (1 + R1/R2) V. Regulators bb-out and ldo1
23 have a fixed 0.8 V reference and thus output 0.8 * (1 + R1/R2) V. The ldo3
24 regulator is fixed to 1.8 V on LTC3589 and to 2.8 V on LTC3589-1,2. The ldo4
25 regulator can output between 1.8 V and 3.3 V on LTC3589 and between 1.2 V
26 and 3.2 V on LTC3589-1,2 in four steps. The ldo1 standby regulator can not
|
| /Documentation/litmus-tests/atomic/ |
| D | Atomic-RMW-ops-are-atomic-WRT-atomic_set.litmus | 11 atomic_t v = ATOMIC_INIT(1);
14 P0(atomic_t *v)
16 (void)atomic_add_unless(v, 1, 0);
19 P1(atomic_t *v)
21 atomic_set(v, 0);
25 (v=2)
|
| /Documentation/devicetree/bindings/mfd/ |
| D | maxim,max8998.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
35 maxItems: 2
46 enum: [0, 1, 2, 3]
57 Default voltage setting selected from the possible 2 options selectable
74 maxItems: 2
108 "^(LDO([2-9]|1[0-7])|BUCK[1-4])$":
171 regulator-name = "VALIVE_1.2V";
178 regulator-name = "VUSB+MIPI_1.1V";
185 regulator-name = "VADC_3.3V";
191 regulator-name = "VTF_2.8V";
[all …]
|
| /Documentation/devicetree/bindings/display/bridge/ |
| D | chipone,icn6211.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
40 description: A 1.8V/2.5V/3.3V supply that power the MIPI RX.
43 description: A 1.8V/2.5V/3.3V supply that power the PLL.
46 description: A 1.8V/2.5V/3.3V supply that power the RGB output.
69 - const: 2
|
| /Documentation/devicetree/bindings/timer/ |
| D | riscv,timer.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
7 title: RISC-V timer
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14 based on the time CSR defined by the RISC-V privileged specification. The
15 timer interrupts of this device are configured using the RISC-V SBI Time
16 extension or the RISC-V Sstc extension.
18 The clock frequency of RISC-V timer device is specified via the
|
| /Documentation/fb/ |
| D | viafb.modes | 16 # 12 chars 2 lines
18 # 2 chars 10 lines
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
43 # 2 chars 1 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
116 # D: 52.406 MHz, H: 61.800 kHz, V: 120.00 Hz
[all …]
|
| /Documentation/ |
| D | atomic_t.txt | 65 2s-complement.
94 atomic_t v = ATOMIC_INIT(1);
97 P0(atomic_t *v)
99 (void)atomic_add_unless(v, 1, 0);
102 P1(atomic_t *v)
104 atomic_set(v, 0);
108 (v=2)
112 _after_ in which case we'd overwrite its result. In no case is "2" a valid
123 atomic_add_unless(v, 1, 0);
125 ret = READ_ONCE(v->counter); // == 1
[all …]
|