Searched +full:32 +full:- +full:61 (Results 1 – 25 of 53) sorted by relevance
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| /Documentation/translations/zh_CN/core-api/ |
| D | packing.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/core-api/packing.rst
22 --------
42 --------
46 - 将一个CPU可使用的数字打包到内存缓冲区中（具有硬件约束/特殊性）。
47 - 将内存缓冲区（具有硬件约束/特殊性）解压缩为一个CPU可使用的数字。
61 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
75 56 57 58 59 60 61 62 63 48 49 50 51 52 53 54 55 40 41 42 43 44 45 46 47 32 33 34 35 36 37 38 39
87 39 38 37 36 35 34 33 32 47 46 45 44 43 42 41 40 55 54 53 52 51 50 49 48 63 62 61 60 59 58 57 56
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| /Documentation/core-api/ |
| D | packing.rst | 6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
37 into a CPU-usable number.
55 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
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| /Documentation/devicetree/bindings/clock/ |
| D | imx28-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx28-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
18 ------------------
51 emi_pll 32
80 usb1 61
87 const: fsl,imx28-clkctrl
92 '#clock-cells':
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| D | st,nomadik.txt | 4 Documentation/devicetree/bindings/clock/clock-bindings.txt
10 - compatible: must be "stericsson,nomadik-src"
11 - reg: must contain the SRC register base and size
14 - disable-sxtalo: if present this will disable the SXTALO
15 i.e. the driver output for the slow 32kHz chrystal, if the
17 - disable-mxtal: if present this will disable the MXTALO,
28 - compatible: must be "st,nomadik-pll-clock"
29 - clock-cells: must be 0
30 - clock-id: must be 1 or 2 for PLL1 and PLL2 respectively
31 - clocks: this clock will have main chrystal as parent
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| D | imx35-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx35-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steffen Trumtrar <s.trumtrar@pengutronix.de>
18 ---------------------------
51 audmux_gate 32
80 rngc_gate 61
105 const: fsl,imx35-ccm
113 '#clock-cells':
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| D | alphascale,acc.txt | 7 - compatible: must be "alphascale,asm9260-clock-controller"
8 - reg: must contain the ACC register base and size
9 - #clock-cells : shall be set to 1.
11 Simple one-cell clock specifier format is used, where the only cell is used
13 It is encouraged to use dt-binding for clock index definitions. SoC specific
14 dt-binding should be included to the device tree descriptor. For example
16 #include <dt-bindings/clock/alphascale,asm9260.h>
19 _AHB_ - AHB gate;
20 _SYS_ - adjustable clock source. Not all peripheral have _SYS_ clock provider.
54 CLKID_AHB_CAMIF 32
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| D | imx25-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx25-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sascha Hauer <s.hauer@pengutronix.de>
18 --------------------------
51 per6 32
80 emi_ahb 61
152 const: fsl,imx25-ccm
160 '#clock-cells':
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| D | st,stm32mp25-rcc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/st,stm32mp25-rcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gabriel Fernandez <gabriel.fernandez@foss.st.com>
17 include/dt-bindings/clock/st,stm32mp25-rcc.h
18 include/dt-bindings/reset/st,stm32mp25-rcc.h
23 - st,stm32mp25-rcc
28 '#clock-cells':
31 '#reset-cells':
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| /Documentation/bpf/ |
| D | llvm_reloc.rst | 1 .. SPDX-License-Identifier: (LGPL-2.1 OR BSD-2-Clause)
12 LLVM BPF backend records each relocation with the following 16-byte
31 Compiled with ``clang --target=bpf -O2 -c test.c``, the following is
32 the code with ``llvm-objdump -dr test.o``::
36 2: 61 11 00 00 00 00 00 00 r1 = *(u32 *)(r1 + 0)
39 5: 61 20 00 00 00 00 00 00 r0 = *(u32 *)(r2 + 0)
43 9: 61 11 00 00 00 00 00 00 r1 = *(u32 *)(r1 + 0)
47 13: 61 11 00 00 00 00 00 00 r1 = *(u32 *)(r1 + 0)
52 The following ``llvm-readelf -r test.o`` shows the binary values of the four
66 The following is the symbol table with ``llvm-readelf -s test.o``::
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| /Documentation/translations/zh_CN/infiniband/ |
| D | opa_vnic.rst | 1 .. include:: ../disclaimer-zh_CN.rst
21 太网数据包，支持Omni-Path结构上的以太网功能。
26 Omni-Path封装的以太网数据包的交换模式涉及Omni-Path结构拓扑上覆盖的一个或
27 多个虚拟以太网交换机。Omni-Path结构上的HFI节点的一个子集被允许在特定的虚
35 +-------------------+
39 +-------------------+
44 +-----------------------------+ +------------------------------+
46 | +---------+ +---------+ | | +---------+ +---------+ |
48 +--+---------+----+---------+-+ +-+---------+----+---------+---+
54 +-----------+------------+ +-----------+------------+
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| /Documentation/fb/ |
| D | tgafb.rst | 9 - ZLxP-E1 (8bpp, 2 MB VRAM)
10 - ZLxP-E2 (32bpp, 8 MB VRAM)
11 - ZLxP-E3 (32bpp, 16 MB VRAM, Zbuffer)
20 * Support for fixed-frequency and other oddball monitors
23 User-visible changes since Linux 2.2.x:
25 * Sync-on-green is now handled properly
48 640x480-60, 800x600-56, 640x480-72, 800x600-60, 800x600-72,
49 1024x768-60, 1152x864-60, 1024x768-70, 1024x768-76,
50 1152x864-70, 1280x1024-61, 1024x768-85, 1280x1024-70,
51 1152x864-84, 1280x1024-76, 1280x1024-85
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | loongson,liointc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 This interrupt controller is found in the Loongson-3 family of chips and
14 Loongson-2K series chips, as the primary package interrupt controller which
17 1.The Loongson-2K0500 is a single core CPU;
18 2.The Loongson-2K0500/2K1000 has 64 device interrupt sources as inputs, so we
19 need to define two nodes in dts{i} to describe the "0-31" and "32-61" interrupt
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| /Documentation/devicetree/bindings/net/ |
| D | microchip,sparx5-switch.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
14 The SparX-5 Enterprise Ethernet switch family provides a rich set of
15 Enterprise switching features such as advanced TCAM-based VLAN and
17 security through TCAM-based frame processing using versatile content
25 forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and
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| /Documentation/infiniband/ |
| D | opa_vnic.rst | 2 Intel Omni-Path (OPA) Virtual Network Interface Controller (VNIC)
5 Intel Omni-Path (OPA) Virtual Network Interface Controller (VNIC) feature
6 supports Ethernet functionality over Omni-Path fabric by encapsulating
11 The patterns of exchanges of Omni-Path encapsulated Ethernet packets
12 involves one or more virtual Ethernet switches overlaid on the Omni-Path
13 fabric topology. A subset of HFI nodes on the Omni-Path fabric are
26 +-------------------+
30 +-------------------+
35 +-----------------------------+ +------------------------------+
37 | +---------+ +---------+ | | +---------+ +---------+ |
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| /Documentation/devicetree/bindings/display/imx/ |
| D | fsl,imx-lcdc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx-lcdc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sascha Hauer <s.hauer@pengutronix.de>
11 - Pengutronix Kernel Team <kernel@pengutronix.de>
16 - enum:
17 - fsl,imx1-fb
18 - fsl,imx21-fb
19 - items:
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-davinci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-davinci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Keerthy <j-keerthy@ti.com>
15 - items:
16 - enum:
17 - ti,k2g-gpio
18 - ti,am654-gpio
19 - ti,j721e-gpio
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| /Documentation/devicetree/bindings/dma/ |
| D | stericsson,dma40.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
32 10: Multi-Channel Display Engine MCDE RX
54 32: SD/MMC controller 1
83 61: Crypto Accelerator 0
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| /Documentation/admin-guide/media/ |
| D | tuner-cardlist.rst | 1 .. SPDX-License-Identifier: GPL-2.0
34 25 LG PAL_I+FM (TAPC-I001D)
35 26 LG PAL_I (TAPC-I701D)
41 32 Samsung PAL TCPM9091PD27
49 40 HITACHI V7-J180AT
60 51 Philips PAL/SECAM_D (FM 1256 I-H3)
67 58 Ymec TVision TVF-8531MF/8831MF/8731MF
68 59 Ymec TVision TVF-5533MF
70 61 Tena TNF9533-D/IF/TNF9533-B/DF
73 64 LG TDVS-H06xF
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| D | cx23885-cardlist.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 .. flat-table::
9 :header-rows: 1
11 :stub-columns: 0
13 * - Card number
14 - Card name
15 - PCI subsystem IDs
17 * - 0
18 - UNKNOWN/GENERIC
19 - 0070:3400
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | keystone-navigator-qmss.txt | 5 multi-core Navigator. QMSS consist of queue managers, packed-data structure
9 management of the packet queues. Packets are queued/de-queued by writing or
20 - compatible : Must be "ti,keystone-navigator-qmss".
21 : Must be "ti,66ak2g-navss-qm" for QMSS on K2G SoC.
22 - clocks : phandle to the reference clock for this device.
23 - queue-range : <start number> total range of queue numbers for the device.
24 - linkram0 : <address size> for internal link ram, where size is the total
26 - linkram1 : <address size> for external link ram, where size is the total
29 - qmgrs : child node describing the individual queue managers on the
32 -- managed-queues : the actual queues managed by each queue manager
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | marvell,armada-375-pinctrl.txt | 3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6720-pinctrl"
8 - reg: register specifier of MPP registers
48 mpp32 32 gpio, ge1(txd2), spi1(sck), ptp(trig)
77 mpp61 61 gpio, i2c1(sda), uart1(rxd), spi1(cs2), led(p0)
|
| D | marvell,armada-xp-pinctrl.txt | 3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
8 "marvell,mv78460-pinctrl"
9 - reg: register specifier of MPP registers
50 mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk)
53 mpp32 32 gpio, tdm(int3), sd0(d0)
61 mpp40 40 gpio, spi0(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0),
63 mpp41 41 gpio, spi0(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
94 mpp61 61 gpio, dev(ad26)
|
| D | marvell,armada-370-pinctrl.txt | 3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6710-pinctrl"
8 - reg: register specifier of MPP registers
20 mpp4 4 gpio, vdd(cpu-pd)
53 mpp32 32 gpio, spi0(cs0)
91 mpp61 61 gpo, dev(we1), uart1(txd), audio(lrclk)
99 one example of a gpio usage on the board D-Link DNS-327L
|
| D | mediatek,mt7986-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7986-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@kernel.org>
18 - mediatek,mt7986a-pinctrl
19 - mediatek,mt7986b-pinctrl
25 reg-names:
27 - const: gpio
28 - const: iocfg_rt
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| /Documentation/virt/kvm/x86/ |
| D | timekeeping.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Timekeeping Virtualization for X86-Based Architectures
32 information relevant to KVM and hardware-based virtualization.
41 2.1. i8254 - PIT
42 ----------------
46 channels which can be programmed to deliver periodic or one-shot interrupts.
53 The PIT uses I/O ports 0x40 - 0x43. Access to the 16-bit counters is done
57 controlled by port 61h, bit 0, as illustrated in the following diagram::
59 -------------- ----------------
61 | 1.1932 MHz|---------->| CLOCK OUT | ---------> IRQ 0
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