Searched +full:32 +full:- +full:bits (Results 1 – 25 of 369) sorted by relevance
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| /Documentation/filesystems/ext4/ |
| D | group_descr.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 -----------------------
30 block group descriptor was only 32 bytes long and therefore ends at
38 checksum is the lower 16 bits of the checksum of the FS UUID, the group
45 .. list-table::
47 :header-rows: 1
49 * - Offset
50 - Size
51 - Name
52 - Description
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| D | inodes.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 -----------
15 links and is in general more seek-happy than ext4 due to its simpler
22 ``(inode_number - 1) / sb.s_inodes_per_group``, and the offset into the
23 group's table is ``(inode_number - 1) % sb.s_inodes_per_group``. There
31 .. list-table::
33 :header-rows: 1
36 * - Offset
37 - Size
38 - Name
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| D | checksums.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 ---------
10 structures did not have space to fit a full 32-bit checksum, so only the
11 lower 16 bits are stored. Enabling the 64bit feature increases the data
12 structure size so that full 32-bit checksums can be stored for many data
13 structures. However, existing 32-bit filesystems cannot be extended to
18 ``tune2fs -O metadata_csum`` against the underlying device. If tune2fs
20 checksum, it will request that you run ``e2fsck -D`` to have the
30 .. list-table::
32 :header-rows: 1
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| /Documentation/staging/ |
| D | crc32.rst | 5 A CRC is a long-division remainder. You add the CRC to the message,
11 protocols put the end-of-frame flag after the CRC.
15 - We're working in binary, so the digits are only 0 and 1, and
16 - When dividing polynomials, there are no carries. Rather than add and
21 To produce a 32-bit CRC, the divisor is actually a 33-bit CRC polynomial.
22 Since it's 33 bits long, bit 32 is always going to be set, so usually the
24 familiar with the IEEE 754 floating-point format, it's the same idea.)
26 Note that a CRC is computed over a string of *bits*, so you have
27 to decide on the endianness of the bits within each byte. To get
28 the best error-detecting properties, this should correspond to the
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-xilinx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
13 - $ref: spi-controller.yaml#
18 - xlnx,xps-spi-2.00.a
19 - xlnx,xps-spi-2.00.b
20 - xlnx,axi-quad-spi-1.00.a
28 xlnx,num-ss-bits:
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| /Documentation/userspace-api/media/rc/ |
| D | rc-protos.rst | 1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
22 Some remotes have a pointer-type device which can used to control the
29 rc-5 (RC_PROTO_RC5)
30 -------------------
32 This IR protocol uses manchester encoding to encode 14 bits. There is a
38 .. flat-table:: rc5 bits scancode mapping
41 * - rc-5 bit
43 - scancode bit
45 - description
47 * - 1
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| /Documentation/devicetree/bindings/opp/ |
| D | allwinner,sun50i-h6-operating-points.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
20 - $ref: opp-v2-base.yaml#
25 - allwinner,sun50i-h6-operating-points
26 - allwinner,sun50i-h616-operating-points
28 nvmem-cells:
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| /Documentation/locking/ |
| D | robust-futex-ABI.rst | 43 consisting of three words. Each word is 32 bits on 32 bit arch's, or 64
44 bits on 64 bit arch's, and local byte order. Each thread should have
47 If a thread is running in 32 bit compatibility mode on a 64 native arch
48 kernel, then it can actually have two such structures - one using 32 bit
49 words for 32 bit compatibility mode, and one using 64 bit words for 64
50 bit native mode. The kernel, if it is a 64 bit kernel supporting 32 bit
63 is always a 32 bit word, unlike the other words above. The 'lock
64 word' holds 2 flag bits in the upper 2 bits, and the thread id (TID)
65 of the thread holding the lock in the bottom 30 bits. See further
66 below for a description of the flag bits.
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| /Documentation/userspace-api/media/v4l/ |
| D | pixfmt-srggb14p.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB14P:
4 .. _v4l2-pix-fmt-sbggr14p:
5 .. _v4l2-pix-fmt-sgbrg14p:
6 .. _v4l2-pix-fmt-sgrbg14p:
17 14-bit packed Bayer formats
24 bits per colour. Every four consecutive samples are packed into seven
25 bytes. Each of the first four bytes contain the eight high order bits
27 significants bits of each pixel, in the same order.
29 Each n-pixel row contains n/2 green samples and n/2 blue or red samples,
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| D | pixfmt-yuv-planar.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. planar-yuv:
12 - Semi-planar formats use two planes. The first plane is the luma plane and
16 - Fully planar formats use three planes to store the Y, Cb and Cr components
26 and applications that support the multi-planar API, described in
27 :ref:`planar-apis`. Unless explicitly documented as supporting non-contiguous
31 Semi-Planar YUV Formats
46 For non-contiguous formats, no constraints are enforced by the format on the
49 All components are stored with the same number of bits per component.
57 .. flat-table:: Overview of Semi-Planar YUV Formats
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| D | pixfmt-srggb10p.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB10P:
4 .. _v4l2-pix-fmt-sbggr10p:
5 .. _v4l2-pix-fmt-sgbrg10p:
6 .. _v4l2-pix-fmt-sgrbg10p:
16 10-bit packed Bayer formats
23 bits per sample. Every four consecutive samples are packed into 5
24 bytes. Each of the first 4 bytes contain the 8 high order bits
26 bits of each pixel, in the same order.
28 Each n-pixel row contains n/2 green samples and n/2 blue or red samples,
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| D | pixfmt-srggb12p.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB12P:
4 .. _v4l2-pix-fmt-sbggr12p:
5 .. _v4l2-pix-fmt-sgbrg12p:
6 .. _v4l2-pix-fmt-sgrbg12p:
13 12-bit packed Bayer formats
14 ---------------------------
21 bits per colour. Every two consecutive samples are packed into three
22 bytes. Each of the first two bytes contain the 8 high order bits of
24 bits of each pixel, in the same order.
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| /Documentation/devicetree/bindings/arm/ |
| D | qcom,coresight-tpdm.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/qcom,coresight-tpdm.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Trace, Profiling and Diagnostics Monitor - TPDM
13 Basic Counts (BC), Tenure Counts (TC), Continuous Multi-Bit (CMB), and Discrete
22 - Mao Jinlong <quic_jinlmao@quicinc.com>
23 - Tao Zhang <quic_taozha@quicinc.com>
31 - qcom,coresight-tpdm
33 - compatible
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| D | cpus.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
52 required and matches the CPUID[11:0] register bits.
54 Bits [11:0] in the reg cell must be set to
55 bits [11:0] in CPU ID register.
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| /Documentation/arch/x86/ |
| D | zero-page.rst | 1 .. SPDX-License-Identifier: GPL-2.0
6 The additional fields in struct boot_params as a part of 32-bit boot
7 protocol of kernel. These should be filled by bootloader or 16-bit
8 real-mode setup code of the kernel. References/settings to it mainly
28 0C0/004 ALL ext_ramdisk_image ramdisk_image high 32bits
29 0C4/004 ALL ext_ramdisk_size ramdisk_size high 32bits
30 0C8/004 ALL ext_cmd_line_ptr cmd_line_ptr high 32bits
33 1C0/020 ALL efi_info EFI 32 information (struct efi_info)
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| /Documentation/devicetree/bindings/gpio/ |
| D | xlnx,gpio-xilinx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/xlnx,gpio-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neeli Srinivas <srinivas.neeli@amd.com>
14 to an AXI4-Lite interface. The AXI GPIO can be configured as either
15 a single or a dual-channel device. The width of each channel is
22 - xlnx,xps-gpio-1.00.a
27 "#gpio-cells":
33 gpio-controller: true
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| D | gpio-ts4900.txt | 1 * Technologic Systems I2C-FPGA's GPIO controller bindings
4 TS-4900's FPGA encodes the GPIO state on 3 bits, whereas the TS-7970's FPGA
5 uses 2 bits: it doesn't use a dedicated input bit.
8 - compatible: Should be one of the following
9 "technologic,ts4900-gpio"
10 "technologic,ts7970-gpio"
11 - reg: Physical base address of the controller and length
13 - #gpio-cells: Should be two. The first cell is the pin number.
14 - gpio-controller: Marks the device node as a gpio controller.
17 - ngpios: Number of GPIOs this controller is instantiated with,
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| /Documentation/devicetree/bindings/perf/ |
| D | riscv,pmu.yaml | 1 # SPDX-License-Identifier: BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V SBI PMU events
10 - Atish Patra <atishp@rivosinc.com>
31 https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc
37 riscv,event-to-mhpmevent:
38 $ref: /schemas/types.yaml#/definitions/uint32-matrix
40 Represents an ONE-to-ONE mapping between a PMU event and the event
48 - description: event_idx, a 20-bit wide encoding of the event type and
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| /Documentation/devicetree/bindings/dma/ |
| D | snps,dma-spear1340.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <vireshk@kernel.org>
11 - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
14 - $ref: dma-controller.yaml#
19 - const: snps,dma-spear1340
20 - items:
21 - enum:
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| /Documentation/devicetree/bindings/display/ |
| D | wm,wm8505-fb.txt | 2 -----------------------------------------------------
5 - compatible : "wm,wm8505-fb"
6 - reg : Should contain 1 register ranges(address and length)
7 - bits-per-pixel : bit depth of framebuffer (16 or 32)
10 - display-timings: see display-timing.txt for information
15 compatible = "wm,wm8505-fb";
17 bits-per-pixel = <16>;
19 display-timings {
20 native-mode = <&timing0>;
22 clock-frequency = <0>; /* unused but required */
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| D | via,vt8500-fb.txt | 2 -----------------------------------------------------
5 - compatible : "via,vt8500-fb"
6 - reg : Should contain 1 register ranges(address and length)
7 - interrupts : framebuffer controller interrupt
8 - bits-per-pixel : bit depth of framebuffer (16 or 32)
11 - display-timings: see display-timing.txt for information
16 compatible = "via,vt8500-fb";
19 bits-per-pixel = <16>;
21 display-timings {
22 native-mode = <&timing0>;
[all …]
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| /Documentation/virt/kvm/arm/ |
| D | ptp_kvm.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 host to the guest using a KVM-specific hypercall.
11 ----------------------------------------
16 +---------------------+-------------------------------------------------------+
18 +---------------------+-------------------------------------------------------+
20 +---------------------+----------+--------------------------------------------+
22 +---------------------+----------+----+---------------------------------------+
24 | | | +---------------------------------------+
26 +---------------------+----------+----+---------------------------------------+
27 | Return Values: | (int32) | R0 | ``NOT_SUPPORTED (-1)`` on error, else |
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| /Documentation/devicetree/bindings/mailbox/ |
| D | arm,mhu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jassi Brar <jaswinder.singh@linaro.org>
13 The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has 3
22 interrupt signal using a 32-bit register, with all 32-bits logically ORed
24 check the status of each of the bits of this register independently. The use
25 of 32 bits per interrupt line enables software to provide more information
28 interrupt. Each of the 32-bits can be used as "doorbell" to alert the remote
37 - arm,mhu
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| /Documentation/bpf/ |
| D | classic_vs_extended.rst | 12 - Number of registers increase from 2 to 10:
15 new layout extends this to be 10 internal registers and a read-only frame
16 pointer. Since 64-bit CPUs are passing arguments to functions via registers
17 the number of args from eBPF program to in-kernel function is restricted
18 to 5 and one register is used to accept return value from an in-kernel
20 sparcv9/mips64 have 7 - 8 registers for arguments; x86_64 has 6 callee saved
25 64-bit architectures.
27 On 32-bit architectures JIT may map programs that use only 32-bit arithmetic
30 R0 - R5 are scratch registers and eBPF program needs spill/fill them if
33 call predefined in-kernel functions, though.
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| /Documentation/bpf/standardization/ |
| D | instruction-set.rst | 27 BCP 14 `<https://www.rfc-editor.org/info/rfc2119>`_
28 `<https://www.rfc-editor.org/info/rfc8174>`_
38 -----
51 .. table:: Meaning of bit-width notation
56 8 8 bits
57 16 16 bits
58 32 32 bits
59 64 64 bits
60 128 128 bits
63 For example, `u32` is a type whose valid values are all the 32-bit unsigned
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