Searched +full:32 +full:khz (Results 1 – 25 of 67) sorted by relevance
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| /Documentation/fb/ |
| D | viafb.modes | 14 # Scan Frequency 31.469 kHz 59.94 Hz
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
30 geometry 640 480 640 480 32
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
33 geometry 480 640 480 640 32 timings 39722 72 24 19 1 48 3 endmode
39 # Scan Frequency 37.500 kHz 75.00 Hz
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
54 geometry 640 480 640 480 32 timings 31747 120 16 16 1 64 3 endmode
60 # Scan Frequency 43.269 kHz 85.00 Hz
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
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| /Documentation/devicetree/bindings/clock/ |
| D | lpc1850-creg-clk.txt | 5 32 kHz oscillator driver with power up/down and clock gating. Next
6 is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.
9 The 32 kHz can also be routed to other peripherals to enable low
21 Shall contain a phandle to the fixed 32 kHz crystal.
28 0 1 kHz clock
29 1 32 kHz Oscillator
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| D | maxim,max77686.txt | 1 Binding for Maxim MAX77686/MAX77802/MAX77620 32k clock generator block
10 The MAX77686 contains three 32.768khz clock outputs that can be controlled
15 The MAX77802 contains two 32.768khz clock outputs that can be controlled
19 The MAX77686 contains one 32.768khz clock outputs that can be controlled
34 - 0: 32khz_ap clock (max77686, max77802), 32khz_out0 (max77620)
35 - 1: 32khz_cp clock (max77686, max77802),
36 - 2: 32khz_pmic clock (max77686).
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| D | clk-palmas-clk32kg-clocks.txt | 1 * Palmas 32KHz clocks *
3 Palmas device has two clock output pins for 32KHz, KG and KG_AUDIO.
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| D | vf610-clock.txt | 16 - sxosc (external crystal oscillator 32KHz, recommended)
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| D | stericsson,u8500-clks.yaml | 17 clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and
92 description: A subnode with zero clock cells for the 32kHz RTC clock.
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| D | st,nomadik.txt | 15 i.e. the driver output for the slow 32kHz chrystal, if the
76 (32, 33, 34, 35 RESERVED)
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| D | st,stm32mp25-rcc.yaml | 39 - description: CK_SCMI_LSE Low Speed External oscillator (32 KHz)
40 - description: CK_SCMI_LSI Low Speed Internal oscillator (~ 32 KHz)
75 - description: CK_SCMI_FLEXGEN_32 flexgen clock 32
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| D | amlogic,meson8b-clkc.txt | 18 * "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN)
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| /Documentation/arch/arm/sunxi/ |
| D | clocks.rst | 18 24MHz 32kHz
26 When you are about to suspend, you switch the CPU Mux to the 32kHz
29 24Mhz 32kHz
39 32kHz
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| /Documentation/ABI/testing/ |
| D | sysfs-class-rtc-rtc0-device-rtc_calibration | 7 calibrate the AB8500.s 32KHz Real Time Clock.
12 30.5 micro-seconds (half-parts-per-million of the 32KHz clock)
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| /Documentation/hwmon/ |
| D | g760a.rst | 24 cycle counts of an assumed 32kHz clock source.
30 from the measured speed pulse period by assuming again a 32kHz clock
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| /Documentation/devicetree/bindings/mfd/ |
| D | max77620.txt | 36 with internal regulators. 32KHz clock can be programmed to be part of a
46 Each regulator, GPIO1, GPIO2, GPIO3, and 32KHz clock has a flexible power
54 When FPS event cleared (set to LOW), regulators, GPIOs and 32KHz
58 and 32KHz clock get disabled at
68 regulators, GPIOs and 32kHz clocks are provided in their respective
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| D | mxs-lradc.txt | 15 Allowed value is 1 ... 32, default is 4
18 2 kHz and its default is 2 (= 1 ms)
20 1 ... 2047. It counts at 2 kHz and its default is
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| /Documentation/devicetree/bindings/rtc/ |
| D | ingenic,rtc.yaml | 68 (assuming RTC clock at 32 kHz)
76 (assuming RTC clock at 32 kHz)
108 interrupts = <32>;
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| D | trivial-rtc.yaml | 23 # AB-RTCMC-32.768kHz-B5ZE-S3: Real Time Clock/Calendar Module with I2C Interface
25 # AB-RTCMC-32.768kHz-EOZ9: Real Time Clock/Calendar Module with I2C Interface
35 # I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output
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| /Documentation/devicetree/bindings/regulator/ |
| D | renesas,raa215300.yaml | 14 32-bit and 64-bit MCU and MPU applications. It supports DDR3, DDR3L, DDR4,
16 built-in Real-Time Clock (RTC), 32kHz crystal oscillator, and coin cell
66 /* 32.768kHz crystal */
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| /Documentation/devicetree/bindings/sound/ |
| D | ics43432.txt | 5 frequency (460 kHz to 3.379 MHz according to the data sheet) there must be
6 64 clock cycles in each stereo output frame; 24 of the 32 available bits
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| /Documentation/sound/cards/ |
| D | hdspm.rst | 37 * Double Speed -- 1..32 channels
42 over the MADI, but all 32 channels are available for the mixer,
54 * Format -- signed 32 Bit Little Endian (SNDRV_PCM_FMTBIT_S32_LE)
143 * Values -- "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz",
144 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz",
145 "Internal 96.0 kHz"
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| /Documentation/dev-tools/ |
| D | gpio-sloppy-logic-analyzer.rst | 54 maximum of 8 probes are supported. 32 are likely possible but are not
67 snippet which analyzes an I2C bus at 400kHz on a Renesas Salvator-XS board, the
70 parameter. The bus speed is 400kHz. So, the sampling theorem says we need to
71 sample at least at 800kHz. However, falling edges of both signals in an I2C
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| /Documentation/devicetree/bindings/pwm/ |
| D | ti,omap-dmtimer-pwm.yaml | 41 0x01 - 32-kHz always-on clock (timer_32k_ck)
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| /Documentation/userspace-api/media/dvb/ |
| D | dmx-get-stc.rst | 39 and a 32 bit denominator, so the real 90kHz STC value is
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| /Documentation/arch/m68k/ |
| D | kernel-options.rst | 308 buffer in kilobytes (minimum 4, default 32) and <catch-radius> says
532 the horizontal frequency, in kHz.
534 The defaults are 58;62;31;32 (VGA compatible).
619 32). Default: 8/1. (Note: Values > 1 seem to cause problems on a
727 - ntsc : 640x200, 15 kHz, 60 Hz
728 - ntsc-lace : 640x400, 15 kHz, 60 Hz interlaced
731 - pal : 640x256, 15 kHz, 50 Hz
732 - pal-lace : 640x512, 15 kHz, 50 Hz interlaced
735 - multiscan : 640x480, 29 kHz, 57 Hz
736 - multiscan-lace : 640x960, 29 kHz, 57 Hz interlaced
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| /Documentation/devicetree/bindings/watchdog/ |
| D | allwinner,sun4i-a10-wdt.yaml | 42 - description: 32 KHz input clock
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| /Documentation/translations/zh_CN/power/ |
| D | energy-model.rst | 171 02 unsigned long *KHz)
176 07 freq = foo_get_freq_ceil(dev, *KHz);
187 18 *KHz = freq;
201 32 nr_opp = foo_get_nr_opp(policy);
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