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/Documentation/hwmon/
Ddme1737.rst63 and SCH5127 Super-I/O chips. These chips feature monitoring of 3 temp sensors
64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and
66 up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and
70 Fan[3-6] and pwm[3,5-6] are optional features and their availability depends on
74 For the SCH311x and SCH5127, fan[1-3] and pwm[1-3] are always present and
94 in0: +5VTR (+5V standby) 0V - 6.64V
95 in1: Vccp (processor core) 0V - 3V
96 in2: VCC (internal +3.3V) 0V - 4.38V
97 in3: +5V 0V - 6.64V
98 in4: +12V 0V - 16V
[all …]
Dltc4245.rst52 in1_input 12v input voltage (mV)
53 in2_input 5v input voltage (mV)
54 in3_input 3v input voltage (mV)
55 in4_input Vee (-12v) input voltage (mV)
57 in1_min_alarm 12v input undervoltage alarm
58 in2_min_alarm 5v input undervoltage alarm
59 in3_min_alarm 3v input undervoltage alarm
60 in4_min_alarm Vee (-12v) input undervoltage alarm
62 curr1_input 12v current (mA)
63 curr2_input 5v current (mA)
[all …]
Dsmsc47m192.rst35 These chips support 3 temperature channels and 8 voltage inputs
45 192 counts, i.e. 3/4 of the full range. Thus the available range for
46 each voltage channel is 0V ... 255/192*(nominal voltage), the resolution
51 The +12V analog voltage input channel (in4_input) is multiplexed with
53 a +12V voltage measurement or a 5 bit CPU VID, but not both.
54 The default setting is to use the pin as 12V input, and use only 4 bit VID.
67 in0_input +2.5V voltage input
68 in1_input CPU voltage input (nominal 2.25V)
69 in2_input +3.3V voltage input
70 in3_input +5V voltage input
[all …]
Dfsp-3y.rst6 * 3Y POWER YH-5151E
7 * 3Y POWER YM-2151E
13 This driver implements limited support for two 3Y POWER devices.
18 * in2_input 12V output voltage
19 * in3_input 5V output voltage
21 * curr2_input 12V output current
22 * curr3_input 5V output current
26 * temp3_input temperature 3
Df71805f.rst48 source), 3 fans and 3 temperature sensors.
68 range is thus from 0 to 2.040 V. Voltage values outside of this range
70 the chip's own power source (+3.3V), and is divided internally by a
83 in0 VCC VCC3.3V int. int. 2.00 1.65 V
84 in1 VIN1 VTT1.2V 10K - 1.00 1.20 V
85 in2 VIN2 VRAM 100K 100K 2.00 ~1.25 V [1]_
86 in3 VIN3 VCHIPSET 47K 100K 1.47 2.24 V [2]_
87 in4 VIN4 VCC5V 200K 47K 5.25 0.95 V
88 in5 VIN5 +12V 200K 20K 11.00 1.05 V
89 in6 VIN6 VCC1.5V 10K - 1.00 1.50 V
[all …]
Dmc13783-adc.rst47 0 Battery Voltage (BATT) 2.50 - 4.65V -2.40V
49 2 Application Supply (BP) 2.50 - 4.65V -2.40V
50 3 Charger Voltage (CHRGRAW) 0 - 10V / /5
51 0 - 20V /10
52 4 Charger Current (CHRGISNSP-CHRGISNSN) -0.25 - 0.25V x4
53 5 General Purpose ADIN5 / Battery Pack Thermistor 0 - 2.30V No
54 6 General Purpose ADIN6 / Backup Voltage (LICELL) 0 - 2.30V / No /
55 1.50 - 3.50V -1.20V
56 7 General Purpose ADIN7 / UID / Die Temperature 0 - 2.30V / No /
57 0 - 2.55V / x0.9 / No
[all …]
Dbt1-pvt.rst68 in0: VDD (processor core) 0.62V - 1.168V
69 in1: Low-Vt (low voltage threshold) 0.62V - 1.168V
70 in2: High-Vt (high voltage threshold) 0.62V - 1.168V
71 in3: Standard-Vt (standard voltage threshold) 0.62V - 1.168V
106 in[0-3]_label RO CPU Voltage sensor (either core or
108 in[0-3]_input RO Measured voltage in millivolts.
109 in[0-3]_min RW Low limit for voltage input.
110 in[0-3]_max RW High limit for voltage input.
111 in[0-3]_min_alarm RO Voltage input alarm. Returns 1 if
114 in[0-3]_max_alarm RO Voltage input alarm. Returns 1 if
/Documentation/userspace-api/media/v4l/
Dsubdev-formats.rst124 :widths: 3 1 4
225 :widths: 36 7 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
262 - 3
291 - r\ :sub:`3`
295 - g\ :sub:`3`
299 - b\ :sub:`3`
336 - r\ :sub:`3`
367 - g\ :sub:`3`
371 - b\ :sub:`3`
404 - g\ :sub:`3`
[all …]
Dpixfmt-packed-hsv.rst14 The *saturation* (s) and the *value* (v) are measured in percentage of the
41 - :cspan:`7` Byte 3
49 - 3
58 - 3
67 - 3
76 - 3
98 - h\ :sub:`3`
107 - s\ :sub:`3`
112 - v\ :sub:`7`
113 - v\ :sub:`6`
[all …]
/Documentation/fb/
Dviafb.modes29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
33 geometry 480 640 480 640 32 timings 39722 72 24 19 1 48 3 endmode
41 # 8 chars 3 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
54 geometry 640 480 640 480 32 timings 31747 120 16 16 1 64 3 endmode
62 # 7 chars 3 lines
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
75 geometry 640 480 640 480 32 timings 27777 80 56 25 1 56 3 endmode
83 # 8 chars 3 lines
[all …]
/Documentation/devicetree/bindings/sound/
Dcs35l32.txt25 3 = Boost voltage fixed at 5 V.
32 3 = Left/right channels VPMON[7:0], STATUS.
40 0 = 3.1V
41 1 = 3.2V
42 2 = 3.3V (Default)
43 3 = 3.4V
46 0 = 3.1V
47 1 = 3.2V
48 2 = 3.3V
49 3 = 3.4V (Default)
[all …]
Dfsl,sgtl5000.yaml51 values from 1.25V to 3V by 250mV steps. If this node is not mentioned
52 or the value is unknown, then the value is set to 1.25V.
58 The LRCLK pad strength. Possible values are: 0, 1, 2 and 3 as per the
61 VDDIO 1.8V 2.5V 3.3V
65 3 = 4.99 mA 8.61 mA 12.05 mA
67 enum: [ 0, 1, 2, 3 ]
71 The SCLK pad strength. Possible values are: 0, 1, 2 and 3 as per the
74 VDDIO 1.8V 2.5V 3.3V
78 3 = 4.99 mA 8.61 mA 12.05 mA
80 enum: [ 0, 1, 2, 3 ]
Dti,ts3a227e.yaml14 The TS3A227E detect headsets of 3-ring and 4-ring standards and
34 - 0 # 2.1 V
35 - 1 # 2.2 V
36 - 2 # 2.3 V
37 - 3 # 2.4 V
38 - 4 # 2.5 V
39 - 5 # 2.6 V
40 - 6 # 2.7 V
41 - 7 # 2.8 V
86 codec: audio-controller@3b {
[all …]
Dti,tlv320dac3100.yaml66 enum: [1, 2, 3]
69 1 or MICBIAS_2_0V - MICBIAS output is powered to 2.0V
70 2 or MICBIAS_2_5V - MICBIAS output is powered to 2.5V
71 3 or MICBIAS_AVDD - MICBIAS output is connected to AVDD
75 enum: [0, 1, 2, 3]
78 0 - 1.35V,
79 1 - 1.5V,
80 2 - 1.65V,
81 3 - 1.8V
Dmaxim,max98090.yaml48 enum: [ 0, 1, 2, 3 ]
49 default: 3
52 0 - 2.2v
53 1 - 2.55v
54 2 - 2.4v
55 3 - 2.8v
/Documentation/devicetree/bindings/iio/dac/
Dadi,ltc2664.yaml14 Analog Devices LTC2664 4 channel, 12-/16-Bit, +-10V DAC
31 v-pos-supply:
34 v-neg-supply:
61 0 - MPS2=GND, MPS1=GND, MSP0=GND (+-10V, reset to 0V)
62 1 - MPS2=GND, MPS1=GND, MSP0=VCC (+-5V, reset to 0V)
63 2 - MPS2=GND, MPS1=VCC, MSP0=GND (+-2.5V, reset to 0V)
64 3 - MPS2=GND, MPS1=VCC, MSP0=VCC (0V to 10, reset to 0V)
65 4 - MPS2=VCC, MPS1=GND, MSP0=GND (0V to 10V, reset to 5V)
66 5 - MPS2=VCC, MPS1=GND, MSP0=VCC (0V to 5V, reset to 0V)
67 6 - MPS2=VCC, MPS1=VCC, MSP0=GND (0V to 5V, reset to 2.5V)
[all …]
Dadi,ad3552r.yaml46 internal reference will be used. External reference must be 2.5V
49 description: Vref I/O driven by internal vref to 2.5V. If not set, Vref pin
59 - 3: high SDO drive strength
61 enum: [0, 1, 2, 3]
102 enum: [0, 1, 2, 3]
107 enum: [0, 1, 2, 3]
147 Rfb1x for: 0 to 2.5 V; 0 to 3V; 0 to 5 V;
148 Rfb2x for: 0 to 10 V; -2.5 to 7.5V; -5 to 5 V;
179 Rfb1x for: 0 to 2.5 V; 0 to 5 V;
180 Rfb2x for: 0 to 10 V; -5 to 5 V;
[all …]
Dadi,ad9739a.yaml15 of synthesizing wideband signals from dc up to 3 GHz.
36 vdd-3p3-supply:
37 description: 3.3V Digital input supply.
40 description: 1.8V Digital input supply.
43 description: 3.3V Analog input supply.
46 description: 1.8V Clock input supply.
65 - vdd-3p3-supply
89 vdd-3p3-supply = <&vdd_3_3>;
/Documentation/devicetree/bindings/mmc/
Dnvidia,tegra20-sdhci.yaml113 description: Specify drive strength calibration offsets for 1.8 V
119 automatic calibration times out on a 1.8 V signaling mode.
122 nvidia,pad-autocal-pull-down-offset-3v3:
123 description: Specify drive strength calibration offsets for 3.3 V
127 nvidia,pad-autocal-pull-down-offset-3v3-timeout:
129 automatic calibration times out on a 3.3 V signaling mode.
141 description: Specify drive strength calibration offsets for 1.8 V
147 automatic calibration times out on a 1.8 V signaling mode.
150 nvidia,pad-autocal-pull-up-offset-3v3:
151 description: Specify drive strength calibration offsets for 3.3 V
[all …]
/Documentation/devicetree/bindings/iio/adc/
Dti,ads1015.yaml60 3: Voltage over AIN2 and AIN3.
75 0: +/- 6.144 V
76 1: +/- 4.096 V
77 2: +/- 2.048 V (default)
78 3: +/- 1.024 V
79 4: +/- 0.512 V
80 5: +/- 0.256 V
91 3: 920
101 3: 64
126 ti,gain = <3>;
/Documentation/devicetree/bindings/media/i2c/
Dthine,thp7312.yaml15 various image processing and correction functions, including 3A control. It
54 1.2V supply for core, PLL, MIPI rx and MIPI tx.
58 Supply for input (RX). 1.8V for MIPI, or 1.8/2.8/3.3V for parallel.
62 Supply for output (TX). 1.8V for MIPI, or 1.8/2.8/3.3V for parallel.
66 Supply for host interface. 1.8V, 2.8V, or 3.3V.
70 Supply for sensor interface. 1.8V, 2.8V, or 3.3V.
74 Supply for GPIO_0. 1.8V, 2.8V, or 3.3V.
78 Supply for GPIO_1. 1.8V, 2.8V, or 3.3V.
211 data-lanes = <4 1 3 2>;
219 data-lanes = <4 2 1 3>;
/Documentation/devicetree/bindings/media/
Dsamsung,s5c73m3.yaml44 description: Analog power supply (1.2V).
47 description: lens power supply (2.8V).
50 description: CIS I/O power supply (1.2V to 1.8V).
53 description: Host I/O power supply (1.8V to 2.8V).
56 description: Digital power supply (1.2V).
59 description: Regulator input power supply (2.8V).
79 - const: 3
129 image-sensor@3c {
142 xshutdown-gpios = <&gpf1 3 GPIO_ACTIVE_LOW>; /* ISP_RESET */
147 data-lanes = <1 2 3 4>;
/Documentation/arch/riscv/
Dvector.rst4 Vector Extension Support for RISC-V Linux
8 order to support the use of the RISC-V Vector Extension.
15 these interfaces is to give init systems a way to modify the availability of V
19 are not portable to non-Linux, nor non-RISC-V environments, so it is discourage
20 to use in a portable code. To get the availability of V in an ELF program,
43 arg: The control argument is a 5-bit value consisting of 3 parts, and
44 accessed by 3 masks respectively.
46 The 3 masks, PR_RISCV_V_VSTATE_CTRL_CUR_MASK,
48 represents bit[1:0], bit[3:2], and bit[4]. bit[1:0] accounts for the
49 enablement status of current thread, and the setting at bit[3:2] takes place
[all …]
/Documentation/virt/hyperv/
Doverview.rst6 enlightened guest on Microsoft's Hyper-V hypervisor. Hyper-V
10 partitions. In this documentation, references to Hyper-V usually
15 Hyper-V runs on x86/x64 and arm64 architectures, and Linux guests
16 are supported on both. The functionality and behavior of Hyper-V is
19 Linux Guest Communication with Hyper-V
21 Linux guests communicate with Hyper-V in four different ways:
24 some guest actions trap to Hyper-V. Hyper-V emulates the action and
29 Hyper-V, passing parameters. Hyper-V performs the requested action
32 Hyper-V. On x86/x64, hypercalls use a Hyper-V specific calling
36 * Synthetic register access: Hyper-V implements a variety of
[all …]
/Documentation/devicetree/bindings/leds/backlight/
Drichtek,rt4831-backlight.yaml44 Backlight OVP level selection, currently support 17V/21V/25V/29V.
48 maximum: 3
58 BIT 0/1/2/3 is used to indicate led channel 1/2/3/4 enable or disable.

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