Searched +full:3 +full:rd (Results 1 – 25 of 76) sorted by relevance
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| /Documentation/devicetree/bindings/mips/cavium/ |
| D | bootbus.txt | 40 - cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS).
50 - cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS).
53 = 2 bytes, 2 = 4 bytes, 3 = 8 bytes).
79 <3 0 0x10000 0x50000000 0>,
92 cavium,t-rd-hld = <35>;
97 cavium,t-rd-dly = <0>;
112 cavium,t-rd-hld = <100>;
117 cavium,t-rd-dly = <0>;
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| /Documentation/devicetree/bindings/dma/ |
| D | apm-xgene-dma.txt | 13 3rd - Descriptor ring command register address space.
16 DMA error reporting interrupt. 2nd, 3rd, 4th and 5th interrupts
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| D | lpc1850-dmamux.txt | 6 - #dma-cells: Should be set to <3>.
8 * 2nd cell contain the mux value (0-3) for the peripheral
9 * 3rd cell contain either 1 or 2 depending on the AHB
39 #dma-cells = <3>;
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| /Documentation/admin-guide/ |
| D | devices.txt | 8 3 = /dev/null Null device
53 3 = /dev/fd3 Controller 0, drive 3, autodetect
57 131 = /dev/fd7 Controller 1, drive 3, autodetect
82 44 = /dev/fd?u1680 3.5" 1680K High Density(3)
86 116 = /dev/fd?u1840 3.5" 1840K High Density(3)
97 (3) Autodetectable format in a High Density (1440K) drive only
106 3 char Pseudo-TTY slaves
115 3 block First MFM, RLL and IDE hard disk/CD-ROM interface
124 63 = /dev/hd?63 63rd partition
136 63 = /dev/tty63 63rd virtual console
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| /Documentation/translations/zh_CN/arch/loongarch/ |
| D | introduction.rst | 148 0x180+n (0≤n≤3) 直接映射配置窗口n DMWn
181 2R Opcode + Rj + Rd
182 3R Opcode + Rk + Rj + Rd
183 4R Opcode + Ra + Rk + Rj + Rd
184 2RI8 Opcode + I8 + Rj + Rd
185 2RI12 Opcode + I12 + Rj + Rd
186 2RI14 Opcode + I14 + Rj + Rd
187 2RI16 Opcode + I16 + Rj + Rd
218 3. 位域操作指令::
262 直接映射虚拟内存通过CSR.DMWn（n=0~3）来进行配置，虚拟地址（VA）和物理地址（PA）
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| /Documentation/translations/zh_TW/arch/loongarch/ |
| D | introduction.rst | 148 0x180+n (0≤n≤3) 直接映射配置窗口n DMWn
181 2R Opcode + Rj + Rd
182 3R Opcode + Rk + Rj + Rd
183 4R Opcode + Ra + Rk + Rj + Rd
184 2RI8 Opcode + I8 + Rj + Rd
185 2RI12 Opcode + I12 + Rj + Rd
186 2RI14 Opcode + I14 + Rj + Rd
187 2RI16 Opcode + I16 + Rj + Rd
218 3. 位域操作指令::
262 直接映射虛擬內存通過CSR.DMWn（n=0~3）來進行配置，虛擬地址（VA）和物理地址（PA）
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| /Documentation/arch/loongarch/ |
| D | introduction.rst | 8 currently 3 variants: a reduced 32-bit version (LA32R), a standard 32-bit
130 0x23 Privileged Resource Configuration 3 PRCFG3
165 0x180+n (0≤n≤3) Direct Mapping Configuration Window n DMWn
177 Configuration 3
189 Configuration 3
212 2R Opcode + Rj + Rd
213 3R Opcode + Rk + Rj + Rd
214 4R Opcode + Ra + Rk + Rj + Rd
215 2RI8 Opcode + I8 + Rj + Rd
216 2RI12 Opcode + I12 + Rj + Rd
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| /Documentation/devicetree/bindings/media/ |
| D | img-ir-rev1.txt | 15 Up to 3 clocks may be specified in the following order:
18 3rd: Power modulation clock.
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| /Documentation/admin-guide/media/ |
| D | technisat.rst | 37 (except ``Simple tuner support`` for ATSC 3rd generation only -> see case 9 please).
96 - AirStar ATSC card 3rd generation:
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| /Documentation/devicetree/bindings/net/ |
| D | calxeda-xgmac.yaml | 28 Can point to at most 3 xgmac interrupts. The 1st one is the main
30 3rd one is the low power state interrupt.
32 maxItems: 3
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| D | qca,qca808x.yaml | 13 QCA808X PHYs can have up to 3 LEDs attached.
14 All 3 LEDs are disabled by default.
15 2 LEDs have dedicated pins with the 3rd LED having the
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| D | hisilicon-femac.txt | 22 The 3rd cell is reset post-delay in micro seconds.
35 resets = <&crg 0xec 0>,<&crg 0xec 3>;
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| D | hisilicon-hix5hd2-gmac.txt | 31 The 3rd cell is reset post-delay in micro seconds.
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| /Documentation/networking/ |
| D | regulatory.rst | 167 .n_reg_rules = 3,
185 struct ieee80211_regdomain *rd;
193 rd = kzalloc(size_of_regd, GFP_KERNEL);
194 if (!rd)
197 memcpy(rd, &mydriver_jp_regdom, sizeof(struct ieee80211_regdomain));
200 memcpy(&rd->reg_rules[i],
203 regulatory_struct_hint(rd);
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| /Documentation/userspace-api/media/v4l/ |
| D | fourcc.rst | 30 3rd character: uncompressed bits-per-pixel 0--9, A--
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | atmel,aic.yaml | 33 const: 3
37 bits[3:0] trigger type and level flags:
42 Valid combinations: 1, 2, 3, 4, 8.
44 The 3rd cell specifies irq priority from 0 (lowest) to 7 (highest).
86 #interrupt-cells = <3>;
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| D | marvell,icu.txt | 87 - #interrupt-cells: The value was 3.
95 The 3rd cell was the type of the interrupt. See arm,gic.txt for
104 #interrupt-cells = <3>;
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| D | apple,aic.yaml | 58 const: 3
70 - 3: virtual guest timer
74 The 3rd cell contains the interrupt flags. This is normally
129 #interrupt-cells = <3>;
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| /Documentation/devicetree/bindings/mailbox/ |
| D | brcm,iproc-flexrm-mbox.txt | 19 channel. This should be 3.
27 The 3rd cell contains MSI timer value representing time for
47 #mbox-cells = <3>;
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| /Documentation/hwmon/ |
| D | abituguru3.rst | 5 * Abit uGuru revision 3 (Hardware Monitor part, reading only)
29 motherboards use the abituguru (without the 3 !) driver.
59 The 3rd revision of the uGuru chip in reality is a Winbond W83L951G.
63 Despite Abit not releasing any information regarding the uGuru revision 3,
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| /Documentation/usb/ |
| D | misc_usbsevseg.rst | 39 3. Set the textmode:
50 For example, to set the 0th and 3rd decimal place
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| /Documentation/devicetree/bindings/phy/ |
| D | apm-xgene-phy.txt | 11 1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI).
19 Two set of 3-tuple setting for each (up to 3)
25 Two set of 3-tuple setting for each (up to 3)
27 - apm,tx-boost-gain : Frequency boost AC (LSB 3-bit) and DC (2-bit)
28 gain control. Two set of 3-tuple setting for each
29 (up to 3) supported link speed on the host. Range is
30 between 0 to 31 in unit of dB. Default is 3.
31 - apm,tx-amplitude : Amplitude control. Two set of 3-tuple setting for
32 each (up to 3) supported link speed on the host.
36 3-tuple setting for each (up to 3) supported link
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| /Documentation/devicetree/bindings/usb/ |
| D | realtek,rts5411.yaml | 53 port@3:
56 3rd downstream facing USB port
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| /Documentation/translations/sp_SP/process/ |
| D | kernel-docs.rst | 92 * Título: **Linux Kernel Development, 3rd Edition**
103 * Título: **Linux Device Drivers, 3rd Edition**
109 :ISBN: 0-596-00590-3
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| /Documentation/devicetree/bindings/mmc/ |
| D | synopsys-dw-mshc.yaml | 52 SDMMC clock phase register, and the 3rd value is the bit shift for the
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