| /Documentation/devicetree/bindings/iio/pressure/ |
| D | honeywell,hsc030pa.yaml | 34 …https://prod-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/products/sensors/pressur…
35 …https://prod-edam.honeywell.com/content/dam/honeywell-edam/sps/siot/en-us/products/sensors/pressur…
65 400MD, 600MD, 001BD, 1.6BD, 2.5BD, 004BD, 2.5MG, 004MG, 006MG,
66 010MG, 016MG, 025MG, 040MG, 060MG, 100MG, 160MG, 250MG, 400MG,
68 250KA, 400KA, 600KA, 001GA, 160LD, 250LD, 400LD, 600LD, 001KD,
70 100KD, 160KD, 250KD, 400KD, 250LG, 400LG, 600LG, 001KG, 1.6KG,
72 160KG, 250KG, 400KG, 600KG, 001GG, 015PA, 030PA, 060PA, 100PA,
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| /Documentation/devicetree/bindings/regulator/ |
| D | richtek,rt6245-regulator.yaml | 55 delay time 0us, 10us, 20us, 40us. If this property is missing then keep
63 Buck switch frequency selection. Each respective value means 400KHz,
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| D | qcom-labibb-regulator.yaml | 27 qcom,soft-start-us:
29 enum: [200, 400, 600, 800]
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| /Documentation/dev-tools/ |
| D | gpio-sloppy-logic-analyzer.rst | 67 snippet which analyzes an I2C bus at 400kHz on a Renesas Salvator-XS board, the
70 parameter. The bus speed is 400kHz. So, the sampling theorem says we need to
76 us assume 15ms here which results in the parameter ``-d 15000``. So,
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| /Documentation/devicetree/bindings/thermal/ |
| D | qcom-spmi-adc-tm-hc.yaml | 78 qcom,hw-settle-time-us:
80 enum: [0, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000, 6000, 8000, 10000]
145 qcom,hw-settle-time-us = <200>;
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| D | qcom-spmi-adc-tm5.yaml | 83 qcom,hw-settle-time-us:
85 … enum: [15, 100, 200, 300, 400, 500, 600, 700, 1000, 2000, 4000, 8000, 16000, 32000, 64000, 128000]
201 qcom,hw-settle-time-us = <200>;
251 qcom,hw-settle-time-us = <200>;
259 qcom,hw-settle-time-us = <200>;
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| /Documentation/devicetree/bindings/usb/ |
| D | ci-hdrc-usb2.yaml | 111 phy-clkgate-delay-us = <400>;
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| D | chipidea,usb2-imx.yaml | 255 phy-clkgate-delay-us = <400>;
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| D | snps,dwc3.yaml | 175 when set core will disable a 400us delay to start Polling LFPS after
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| /Documentation/devicetree/bindings/cpu/ |
| D | idle-states.yaml | 396 entry-latency-us:
400 exit-latency-us:
403 The exit-latency-us duration may be guaranteed only after
404 entry-latency-us has passed.
406 min-residency-us:
412 wakeup-latency-us:
418 entry-latency-us + exit-latency-us
422 systems entry-latency-us + exit-latency-us will exceed
423 wakeup-latency-us by this duration.
434 - entry-latency-us
[all …]
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| /Documentation/scheduler/ |
| D | sched-energy.rst | 99 Let us consider a platform with 12 CPUs, split in 3 performance domains
136 each performance domain since it is the one which will allow us to keep the
151 Let us consider a (fake) platform with 2 independent performance domains
159 below. CPUs 0-3 have a util_avg of 400, 100, 600 and 500 respectively
172 512 =========== - ##- - - - - | 170 | 50 | 512 | 400 |
233 768 ============= * CPU0: 400 / 512 * 300 = 234
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| /Documentation/trace/ |
| D | ftrace.rst | 975 # latency: 259 us, #4/4, CPU#2 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:4)
991 ps-6143 2d... 0us!: trace_hardirqs_off <-__lock_task_sighand
992 ps-6143 2d..1 259us+: trace_hardirqs_on <-_raw_spin_unlock_irqrestore
993 ps-6143 2d..1 263us+: time_hardirqs_on <-_raw_spin_unlock_irqrestore
994 ps-6143 2d..1 306us : <stack trace>
1010 (3.8). Then it displays the max latency in microseconds (259 us). The number
1478 # latency: 16 us, #4/4, CPU#0 | (M:preempt VP:0, KP:0, SP:0 HP:0 #P:4)
1494 <idle>-0 0d.s2 0us+: _raw_spin_lock_irq <-run_timer_softirq
1495 <idle>-0 0dNs3 17us : _raw_spin_unlock_irq <-run_timer_softirq
1496 <idle>-0 0dNs3 17us+: trace_hardirqs_on <-run_timer_softirq
[all …]
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| /Documentation/hwmon/ |
| D | adm9240.rst | 75 ADM9240 has a very fast 320us temperature and voltage measurement cycle
81 LM81 measurement cycle is about once per 400ms including fan speed.
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| /Documentation/networking/dsa/ |
| D | sja1105.rst | 134 Below is an example of configuring a 500 us cyclic schedule on egress port
135 ``swp5``. The traffic class gate for management traffic (7) is open for 100 us,
136 and the gates for all other traffic classes are open for 400 us::
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| /Documentation/devicetree/bindings/iio/temperature/ |
| D | adi,ltc2983.yaml | 62 adi,mux-delay-config-us:
306 24 - Thermistor YSI 400 2.252kohm at 25°C
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| /Documentation/filesystems/xfs/ |
| D | xfs-delayed-logging-design.rst | 177 This "worst case" calculation provides us with the static "unit reservation"
265 To take a new reservation without sleeping requires us to be able to take a
333 of each subsequent transaction, and it's the technique that allows us to
365 Effectively, this gives us the maximum bound of outstanding metadata changes
453 require us to lock every object, format them, and then unlock them again.
474 that does not require us to lock the item to access. This formatting and
604 transaction. The current log write code enables us to do this easily with the
606 the transaction commit record, but tracking this requires us to have a
617 This allows us to unlock the CIL immediately after transfer of all the
791 each, so we in 1.5MB of directory buffers we'd have roughly 400 buffers and a
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| /Documentation/block/ |
| D | bfq-iosched.rst | 29 completion hooks---is, e.g., 1.9 us on an Intel Core i7-2760QM@2.40GHz
35 us (mq-deadline is ~800 LOC, against ~10500 LOC for BFQ).
45 - Intel i7-4850HQ: 400 KIOPS
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| /Documentation/admin-guide/media/ |
| D | bttv.rst | 458 Many thanks to Matrix-Vision for giving us 2 cards for free which made
762 Author of this section: Jon Tombs <jon@gte.esi.us.es>
877 M108-B Bt848 -- FR1236 US [#f2]_, [#f3]_
888 - US site has different drivers for (as of 09/2002):
976 - Cinergy 400 (saa7134), "E877 11(S)", "PM820092D" printed on PCB
1259 US models
1729 - MATRIX Vision for giving us 2 cards for free, which made support of
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| /Documentation/arch/m68k/ |
| D | kernel-options.rst | 381 vertical size of the display is less than 400 pixel rows. Otherwise, the
778 of `VGA8x8` if the vertical size of the display is less than 400 pixel
899 option, please inform us about it by mailing to the Linux/68k kernel
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| /Documentation/admin-guide/pm/ |
| D | intel-speed-select.rst | 14 - https://www.intel.com/content/www/us/en/architecture-and-technology/speed-select-technology-artic…
598 While running the above test, if we take turbostat output, it will show us that
651 400 MHz.
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| D | amd-pstate.rst | 484 maximum transition latency: 131 us
485 hardware limits: 400 MHz - 4.68 GHz
487 current policy: frequency should be within 400 MHz and 4.68 GHz.
498 AMD PSTATE Lowest Performance: 15. Lowest Frequency: 400 MHz.
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| /Documentation/driver-api/media/drivers/ |
| D | cx2341x-devel.rst | 195 - Write 0x80000640 to register 0x07F8 to init the Encoder SDRAM's refresh to 1us.
197 - Write 0x80000640 to register 0x08F8 to init the Decoder SDRAM's refresh to 1us.
1156 peak bitrate in bits per second, divided by 400
1161 Mux bitrate in bits per second, divided by 400. May be 0 (default).
1535 '01' 50/15uS
1655 struct info index[400];
1676 Elements requested (up to 400)
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| /Documentation/sound/ |
| D | alsa-configuration.rst | 281 Module for ATI IXP 150/200/250/400 AC97 controllers.
2137 my guest. Remember, the idea is to get a number that causes us
2343 Module for Tascam USB US-122, US-224 and US-428 devices.
2389 sample rates (e.g. 44.1kHz of mp3 playback), please let us
2399 In any cases, please let us know the result and the
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| /Documentation/RCU/Design/Requirements/ |
| D | Requirements.rst | 251 which brings us to the publish-subscribe guarantee discussed in the next
1133 less than 400 milliseconds makes no sense because this would mean that a
2297 issues <https://lore.kernel.org/r/20050318002026.GA2693@us.ibm.com>`__
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