Searched full:48 (Results 1 – 25 of 268) sorted by relevance
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| /Documentation/devicetree/bindings/timer/ |
| D | renesas,cmt.yaml | 14 The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock
29 - renesas,r8a7740-cmt1 # 48-bit CMT1 on R-Mobile A1
34 - renesas,sh73a0-cmt1 # 48-bit CMT1 on SH-Mobile AG5
56 - renesas,r8a73a4-cmt1 # 48-bit CMT1 on R-Mobile APE6
57 - renesas,r8a7742-cmt1 # 48-bit CMT1 on RZ/G1H
58 - renesas,r8a7743-cmt1 # 48-bit CMT1 on RZ/G1M
59 - renesas,r8a7744-cmt1 # 48-bit CMT1 on RZ/G1N
60 - renesas,r8a7745-cmt1 # 48-bit CMT1 on RZ/G1E
61 - renesas,r8a77470-cmt1 # 48-bit CMT1 on RZ/G1C
62 - renesas,r8a7790-cmt1 # 48-bit CMT1 on R-Car H2
[all …]
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| /Documentation/devicetree/bindings/mtd/ |
| D | microchip,mchp48l640.yaml | 7 title: Microchip 48l640 (and similar) serial EERAM
13 The Microchip 48l640 is a 8KByte EERAM connected via SPI.
20 - const: microchip,48l640
41 compatible = "microchip,48l640";
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| /Documentation/devicetree/bindings/sound/ |
| D | ti,j721e-cpb-audio.yaml | 18 In order to support 48KHz and 44.1KHz family of sampling rates the parent
19 clock for AUDIO_REFCLK2 needs to be changed between PLL4 (for 48KHz) and
24 48KHz family:
33 48KHz family:
85 - description: Parent for CPB_McASP auxclk (for 48KHz)
88 - description: Parent for CPB_SCKI clock (for 48KHz)
111 - description: Parent for CPB_McASP auxclk (for 48KHz)
113 - description: Parent for CPB_SCKI clock (for 48KHz)
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| D | ti,j721e-cpb-ivi-audio.yaml | 23 In order to support 48KHz and 44.1KHz family of sampling rates the parent clock
24 for AUDIO_REFCLK0 needs to be changed between PLL4 (for 48KHz) and PLL15 (for
30 Clocking setup for 48KHz family:
76 - description: Parent for CPB_McASP auxclk (for 48KHz)
79 - description: Parent for CPB_SCKI clock (for 48KHz)
82 - description: Parent for IVI_McASP auxclk (for 48KHz)
85 - description: Parent for IVI_SCKI clock (for 48KHz)
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| D | cs4349.txt | 15 codec: cs4349@48 {
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| D | sprd-mcdt.txt | 18 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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| /Documentation/translations/zh_CN/core-api/ |
| D | packing.rst | 61 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
75 56 57 58 59 60 61 62 63 48 49 50 51 52 53 54 55 40 41 42 43 44 45 46 47 32 33 34 35 36 37 38 39
87 39 38 37 36 35 34 33 32 47 46 45 44 43 42 41 40 55 54 53 52 51 50 49 48 63 62 61 60 59 58 57 56
100 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
112 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
124 56 57 58 59 60 61 62 63 48 49 50 51 52 53 54 55 40 41 42 43 44 45 46 47 32 33 34 35 36 37 38 39
134 39 38 37 36 35 34 33 32 47 46 45 44 43 42 41 40 55 54 53 52 51 50 49 48 63 62 61 60 59 58 57 56
145 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
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| /Documentation/devicetree/bindings/net/ |
| D | icplus-ip101ag.txt | 6 - IP101GA (48-pin LQFP package)
10 - IP101A (48-pin LQFP package)
11 - IP101AH (48-pin LQFP package)
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| /Documentation/arch/arm64/ |
| D | memory.rst | 12 with the 4KB page configuration, allowing 39-bit (512GB) or 48-bit
27 AArch64 Linux memory layout with 4KB pages + 4 levels (48-bit)::
64 |63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
79 |63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
86 | +-------------------------------> [47:42] L1 index (48-bit)
106 binary that supports 52-bit must also be able to fall back to 48-bit
110 higher addresses such that they are invariant to 48/52-bit VAs. Due
113 kernel VA space for both 48/52-bit. (Switching from 48-bit to 52-bit,
123 As a single binary will need to support both 48-bit and 52-bit VA
145 VA space maximum size of 48-bits, the kernel will, by default,
[all …]
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| D | kasan-offsets.sh | 14 print_kasan_offset 48 3
22 print_kasan_offset 48 4
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| /Documentation/staging/ |
| D | static-keys.rst | 232 ffffffff81044291: 48 89 e5 mov %rsp,%rbp
234 ffffffff81044299: 65 48 8b 04 25 c0 b6 mov %gs:0xb6c0,%rax
236 ffffffff810442a2: 48 8b 80 80 02 00 00 mov 0x280(%rax),%rax
237 ffffffff810442a9: 48 8b 80 b0 02 00 00 mov 0x2b0(%rax),%rax
238 ffffffff810442b0: 48 8b b8 e8 02 00 00 mov 0x2e8(%rax),%rdi
241 ffffffff810442bd: 48 98 cltq
243 ffffffff810442c0: 48 c7 c7 e3 54 98 81 mov $0xffffffff819854e3,%rdi
253 ffffffff810441f7: 48 89 e5 mov %rsp,%rbp
256 ffffffff810441fe: 65 48 8b 04 25 c0 b6 mov %gs:0xb6c0,%rax
258 ffffffff81044207: 48 8b 80 80 02 00 00 mov 0x280(%rax),%rax
[all …]
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| /Documentation/core-api/ |
| D | packing.rst | 55 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
71 56 57 58 59 60 61 62 63 48 49 50 51 52 53 54 55 40 41 42 43 44 45 46 47 32 33 34 35 36 37 38 39
84 39 38 37 36 35 34 33 32 47 46 45 44 43 42 41 40 55 54 53 52 51 50 49 48 63 62 61 60 59 58 57 56
98 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
110 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
125 56 57 58 59 60 61 62 63 48 49 50 51 52 53 54 55 40 41 42 43 44 45 46 47 32 33 34 35 36 37 38 39
136 39 38 37 36 35 34 33 32 47 46 45 44 43 42 41 40 55 54 53 52 51 50 49 48 63 62 61 60 59 58 57 56
147 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
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| /Documentation/sound/cards/ |
| D | audiophile-usb.rst | 57 * 16-bit/48kHz ==> 4 channels in + 4 channels out
61 * 24-bit/48kHz ==> 4 channels in + 2 channels out,
197 - 16bits 48kHz mode with Di disabled
204 - 16bits 48kHz mode with Di enabled
234 - 24bits 48kHz mode with Di disabled
241 - 24bits 48kHz mode with Di enabled
266 - 16bits 48kHz mode with only the Do port enabled
351 - Otherwise the sample rate range is 8-48kHz
436 - 24-bit depth, 8-48kHz sample mode
441 - 24-bit depth, 8-48kHz sample mode
[all …]
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| /Documentation/devicetree/bindings/hwmon/ |
| D | lm75.yaml | 83 sensor@48 {
95 temperature-sensor@48 {
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| D | adi,ltc2991.yaml | 88 hwmon@48 {
99 hwmon@48 {
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| /Documentation/devicetree/bindings/misc/ |
| D | idt,89hpesx.yaml | 24 - pattern: '^idt,89hpes(6t6g2|16t7|(24t6|32t8|48t12|16t4a?)(g2)?)$'
26 - pattern: '^idt,89hpes((32h8|48h12a?|22h16|34h16|64h16a?)(g2)?|16h16)$'
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| /Documentation/devicetree/bindings/input/touchscreen/ |
| D | max11801-ts.txt | 11 max11801: touchscreen@48 {
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| D | sx8654.txt | 17 sx8654@48 {
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| D | melfas_mip4.txt | 13 touchscreen: melfas_mip4@48 {
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| /Documentation/hwmon/ |
| D | peci-dimmtemp.rst | 14 Intel Xeon E7-48xx v3 family
20 Intel Xeon E7-48xx v4 family
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| D | max31760.rst | 28 reading as an index to a 48-byte lookup table (LUT) containing
54 48 PWM value for T ≥ +110°C
75 pwm1_auto_point[1-48]_pwm PWM value for LUT point
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| /Documentation/devicetree/bindings/clock/ |
| D | silabs,si5341.txt | 54 example, to create 14GHz from a 48MHz xtal, use m-num=14000 and m-den=48. Only
99 /* 48MHz reference crystal */
118 silabs,pll-m-den = <48>;
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| /Documentation/translations/zh_TW/arch/arm64/ |
| D | memory.txt | 40 分別都有 39-bit (512GB) 或 48-bit (256TB) 的虛擬地址空間。
43 用戶地址空間的 63:48 位爲 0，而內核地址空間的相應位爲 1。TTBRx 的
87 |63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
102 |63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
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| /Documentation/translations/zh_CN/arch/arm64/ |
| D | memory.txt | 36 分别都有 39-bit (512GB) 或 48-bit (256TB) 的虚拟地址空间。
39 用户地址空间的 63:48 位为 0，而内核地址空间的相应位为 1。TTBRx 的
83 |63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
98 |63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-xgene.txt | 4 This gpio controller controls a total of 48 gpios.
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