| /Documentation/devicetree/bindings/mfd/ |
| D | omap-usb-host.txt | 24 "ohci-phy-4pin-dpdm",
28 "ohci-tll-4pin-dpdm",
40 * "usbhost_120m_fck" - 120MHz Functional clock.
43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
53 * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
54 * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
[all …]
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| /Documentation/userspace-api/media/dvb/ |
| D | fe-bandwidth-t.rst | 30 - .. _BANDWIDTH-1-712-MHZ:
34 - 1.712 MHz
36 - .. row 4
38 - .. _BANDWIDTH-5-MHZ:
42 - 5 MHz
46 - .. _BANDWIDTH-6-MHZ:
50 - 6 MHz
54 - .. _BANDWIDTH-7-MHZ:
58 - 7 MHz
62 - .. _BANDWIDTH-8-MHZ:
[all …]
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| D | fe_property_parameters.rst | 63 typically 6MHz.
89 DMTB 4-QAM, 16-QAM, 32-QAM, 64-QAM and 4-QAM-NR.
127 ATSC (version 1) No need to set. It is always 6MHz.
128 DMTB No need to set. It is always 8MHz.
129 DVB-T 6MHz, 7MHz and 8MHz.
130 DVB-T2 1.172 MHz, 5MHz, 6MHz, 7MHz, 8MHz and 10MHz
131 ISDB-T 5MHz, 6MHz, 7MHz and 8MHz, although most places
132 use 6MHz.
474 Possible values: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, -1 (AUTO)
528 - .. row 4
[all …]
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| /Documentation/fb/ |
| D | viafb.modes | 10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]
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| /Documentation/devicetree/bindings/net/ |
| D | micrel.txt | 14 KSZ8021: register 0x1f, bits 5..4
15 KSZ8031: register 0x1f, bits 5..4
16 KSZ8051: register 0x1f, bits 5..4
17 KSZ8081: register 0x1f, bits 5..4
18 KSZ8091: register 0x1f, bits 5..4
23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
24 bit selects 25 MHz mode
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
27 than 50 MHz clock mode.
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| D | adi,adin.yaml | 36 enum: [ 4, 8, 12, 16, 20, 24 ]
42 A 25MHz reference and a free-running 125MHz.
44 the 125MHz clocks based on its internal state.
47 - 25mhz-reference
48 - 125mhz-free-running
52 description: Enable 25MHz reference clock output on CLK25_REF pin.
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| D | qcom,ipq4019-mdio.yaml | 42 - description: MDIO clock source frequency fixed to 100MHZ
53 MDC rate is feed by an external clock (fixed 100MHz) and is divider
57 To follow 802.3 standard that instruct up to 2.5MHz by default, if
59 default 1.5625Mhz is select.
116 ethphy4: ethernet-phy@4 {
117 reg = <4>;
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| D | nxp,tja11xx.yaml | 54 typically derived from an external 25MHz crystal. Alternatively,
55 a 50MHz clock signal generated by an external oscillator can be
56 connected to pin REF_CLK. A third option is to connect a 25MHz
91 tja1101_phy0: ethernet-phy@4 {
102 tja1102_phy0: ethernet-phy@4 {
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| /Documentation/admin-guide/pm/ |
| D | intel-speed-select.rst | 74 TDP level change control is unlocked, max level: 4
105 get-config-levels:4
109 get-config-levels:4
111 On this system under test, there are 4 performance profiles in addition to the
152 enable-cpu-list:0,1,2,3,4,5,6,7,8,9,10,11,12,13,28,29,30,31,32,33,34,35,36,37,38,39,40,41
154 base-frequency(MHz):2600
168 condition is met, then base frequency of 2600 MHz can be maintained. To
170 level 4::
172 # intel-speed-select perf-profile info -l 4
178 perf-profile-level-4
[all …]
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| /Documentation/scsi/ |
| D | dc395x.rst | 34 shortcut for dc395x=7,4,9,15,2,10
45 0 20 Mhz
46 1 12.2 Mhz
47 2 10 Mhz
48 3 8 Mhz
49 4 6.7 Mhz
51 6 5 Mhz
52 7 4 Mhz
65 2 0x04 4 Disconnection
67 4 0x10 16 Tagged Command Queueing
[all …]
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| D | aic7xxx.rst | 15 4. Contacting Adaptec
26 aic7770 10 EISA/VL 10MHz 16Bit 4 1
27 aic7850 10 PCI/32 10MHz 8Bit 3
28 aic7855 10 PCI/32 10MHz 8Bit 3
29 aic7856 10 PCI/32 10MHz 8Bit 3
30 aic7859 10 PCI/32 20MHz 8Bit 3
31 aic7860 10 PCI/32 20MHz 8Bit 3
32 aic7870 10 PCI/32 10MHz 16Bit 16
33 aic7880 10 PCI/32 20MHz 16Bit 16
34 aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8
[all …]
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| /Documentation/devicetree/bindings/clock/ |
| D | armada3700-periph-clock.txt | 19 4 tsecm Security Engine
36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
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| D | maxim,max9485.txt | 3 This device exposes 4 clocks in total:
5 - MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
15 - clocks: Input clock, must provide 27.000 MHz
34 xo-27mhz: xo-27mhz {
45 clocks = <&xo-27mhz>;
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| D | samsung,exynosautov920-clock.yaml | 19 two external clocks:: OSCCLK/XTCXO (38.4 MHz) and RTCCLK/XrtcXTI (32768 Hz).
43 maxItems: 4
47 maxItems: 4
66 - description: External reference clock (38.4 MHz)
84 - description: External reference clock (38.4 MHz)
105 - description: External reference clock (38.4 MHz)
123 - description: External reference clock (38.4 MHz)
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| /Documentation/devicetree/bindings/regulator/ |
| D | maxim,max8952.yaml | 26 minItems: 4
27 maxItems: 4
32 Array of 4 integer values defining DVS voltages in microvolts. All values
42 enum: [0, 1, 2, 3, 4, 5, 6, 7]
49 - 3: 4mV/us
50 - 4: 2mV/us
62 - 0: 26 MHz
63 - 1: 13 MHz
64 - 2: 19.2 MHz
65 Defaults to 26 MHz if not specified.
[all …]
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| D | mps,mpq7920.yaml | 27 after their hardware counterparts BUCK[1-4], one LDORTC, and LDO[2-5]
36 1.1MHz, 1.65MHz, 2.2MHz, 2.75MHz
44 "^ldo[1-4]$":
49 "^buck[1-4]$":
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| /Documentation/admin-guide/media/ |
| D | dvb_intro.rst | 107 Seven 177.500 Mhz
108 SBS 184.500 Mhz
109 Nine 191.625 Mhz
110 Ten 219.500 Mhz
111 ABC 226.500 Mhz
112 Channel 31 557.625 Mhz
133 T 177500000 7MHz AUTO AUTO QAM64 8k 1/16 NONE
134 T 184500000 7MHz AUTO AUTO QAM64 8k 1/8 NONE
135 T 191625000 7MHz AUTO AUTO QAM64 8k 1/16 NONE
136 T 219500000 7MHz AUTO AUTO QAM64 8k 1/16 NONE
[all …]
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | sony,imx415.yaml | 31 description: Input clock (24 MHz, 27 MHz, 37.125 MHz, 72 MHz or 74.25 MHz)
66 - const: 4
108 data-lanes = <1 2 3 4>;
|
| D | sony,imx412.yaml | 34 description: Clock frequency 6MHz, 12MHz, 18MHz, 24MHz or 27MHz
96 data-lanes = <1 2 3 4>;
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| /Documentation/userspace-api/media/drivers/ |
| D | max2175.rst | 17 :widths: 1 4
31 :widths: 1 4
48 :widths: 1 4
53 samples/sec with a 10.24 MHz sck.
56 samples/sec with a 32.768 MHz sck.
61 samples/sec with a 14.88375 MHz sck.
64 samples/sec with a 7.441875 MHz sck.
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| /Documentation/devicetree/bindings/cpu/ |
| D | cpu-capacity.txt | 38 by the frequency (in MHz) at which the benchmark has been run, so that
39 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
55 mhz values (normalized w.r.t. the highest value found while parsing the DT).
58 4 - Examples
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
128 capacity-dmips-mhz = <1024>;
[all …]
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | ti,sn65dsi86.yaml | 56 be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4 MHz.
121 - minItems: 4
122 maxItems: 4
131 If you have 4 logical lanes the bridge supports
136 maxItems: 4
240 interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>;
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| /Documentation/devicetree/bindings/clock/st/ |
| D | st,quadfs.txt | 5 or 660MHz (from a 30MHz oscillator input) as the input to the digital
27 - clock-output-names : From common clock binding. The block has 4
32 4 strings are provided then no clocks will be created
|
| /Documentation/devicetree/bindings/input/ |
| D | iqs626a.yaml | 50 description: Divides the device's core clock by a factor of 4.
60 enum: [0, 1, 2, 3, 4, 5, 6, 7]
69 4: 89
84 enum: [0, 1, 2, 3, 4, 5, 6, 7]
93 4: Generic channel 0
112 description: Multiplies all touch and deep-touch thresholds by 4.
260 limited to 4 in the case of the ULP channel, and the property is un-
283 0: 4 MHz (1 MHz)
284 1: 2 MHz (500 kHz)
285 2: 1 MHz (250 kHz)
[all …]
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| /Documentation/devicetree/bindings/display/mediatek/ |
| D | mediatek,dp.yaml | 67 0 1 2 3 - For 4 lanes enabled in IP.
69 maxItems: 4
77 max-linkrate-mhz:
86 - max-linkrate-mhz
99 max-linkrate-mhz = <8100>;
|