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/Documentation/i2c/
Di2c_bus.svg33 …d="m -2.5,-1 c 0,2.76 -2.24,5 -5,5 -2.76,0 -5,-2.24 -5,-5 0,-2.76 2.24,-5 5,-5 2.76,0 5,2.24 5,5 z"
49 …d="m -2.5,-1 c 0,2.76 -2.24,5 -5,5 -2.76,0 -5,-2.24 -5,-5 0,-2.76 2.24,-5 5,-5 2.76,0 5,2.24 5,5 z"
64 …d="m -2.5,-1 c 0,2.76 -2.24,5 -5,5 -2.76,0 -5,-2.24 -5,-5 0,-2.76 2.24,-5 5,-5 2.76,0 5,2.24 5,5 z"
79 …d="m -2.5,-1 c 0,2.76 -2.24,5 -5,5 -2.76,0 -5,-2.24 -5,-5 0,-2.76 2.24,-5 5,-5 2.76,0 5,2.24 5,5 z"
109 d="M 5.77,0 -2.88,5 V -5 Z"
124 d="M 5.77,0 -2.88,5 V -5 Z"
139 d="M 5.77,0 -2.88,5 V -5 Z"
154 …d="m -2.5,-1 c 0,2.76 -2.24,5 -5,5 -2.76,0 -5,-2.24 -5,-5 0,-2.76 2.24,-5 5,-5 2.76,0 5,2.24 5,5 z"
244 d="M 5.77,0 -2.88,5 V -5 Z"
260 d="M 5.77,0 -2.88,5 V -5 Z"
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/Documentation/hwmon/
Ducd9200.rst73 in[2-5]_label "vout[1-4]".
74 in[2-5]_input Measured voltage. From READ_VOUT register.
75 in[2-5]_min Minimum Voltage. From VOUT_UV_WARN_LIMIT register.
76 in[2-5]_max Maximum voltage. From VOUT_OV_WARN_LIMIT register.
77 in[2-5]_lcrit Critical minimum Voltage. VOUT_UV_FAULT_LIMIT register.
78 in[2-5]_crit Critical maximum voltage. From VOUT_OV_FAULT_LIMIT
80 in[2-5]_min_alarm Voltage low alarm. From VOLTAGE_UV_WARNING status.
81 in[2-5]_max_alarm Voltage high alarm. From VOLTAGE_OV_WARNING status.
82 in[2-5]_lcrit_alarm Voltage critical low alarm. From VOLTAGE_UV_FAULT
84 in[2-5]_crit_alarm Voltage critical high alarm. From VOLTAGE_OV_FAULT
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/Documentation/userspace-api/media/v4l/
Dconstraints.svg3 …><path id="path6263" transform="matrix(-.4 0 0 -.4 -4 0)" d="m0 0 5-5-17.5 5 17.5 5-5-5z" fill="#f…
4 …5-5-17.5 5 17.5 5-5-5z" fill="#f00" fill-rule="evenodd" stroke="#f00" stroke-width="1pt"/></marker…
5 …5-5-17.5 5 17.5 5-5-5z" fill="#000080" fill-rule="evenodd" stroke="#000080" stroke-width="1pt"/></…
Dpixfmt-srggb14p.rst65 B\ :sub:`00low bits 5--0`\ (bits 5--0)
69 G\ :sub:`01low bits 5--2`\ (bits 3--0)
71 - G\ :sub:`03low bits 5--0`\ (bits 7--2)
73 B\ :sub:`02low bits 5--4`\ (bits 1--0)
89 G\ :sub:`10low bits 5--0`\ (bits 5--0)
93 R\ :sub:`11low bits 5--2`\ (bits 3--0)
95 - R\ :sub:`13low bits 5--0`\ (bits 7--2)
97 G\ :sub:`12low bits 5--4`\ (bits 1--0)
113 B\ :sub:`20low bits 5--0`\ (bits 5--0)
117 G\ :sub:`21low bits 5--2`\ (bits 3--0)
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Dsubdev-formats.rst199 For instance, a format where pixels are encoded as 5-bits red, 5-bits
200 green and 5-bit blue values padded on the high bit, transferred as 2
260 - 5
617 - g\ :sub:`5`
662 - g\ :sub:`5`
769 - g\ :sub:`5`
806 - g\ :sub:`5`
913 - g\ :sub:`5`
935 - r\ :sub:`5`
941 - g\ :sub:`5`
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/Documentation/driver-api/media/drivers/
Dsh_mobile_ceu_camera.rst26 +-5-- . -- -3-- -\
36 +-5'- .´ -/
51 S_CROP(left / top = (5) - (1), width / height = (5') - (5))
62 (5) to (5') - reverse sensor scale applied to CEU cropped width or height
63 (2) to (5) - reverse sensor scale applied to CEU cropped left or top
79 width_u = (5') - (5) = ((4') - (4)) * scale_s
91 5. Apply iterative sensor S_FMT for sensor output window.
105 left_ceu = (4)_new - (3)_new = ((5) - (2)) / scale_s_new
132 to 2 : 2', target crop 5 : 5', current output format 6' - 6.
138 intermediate window: 4' - 4 = (5' - 5) * (3' - 3) / (2' - 2)
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/Documentation/translations/zh_CN/core-api/
Dpacking.rst62 7 6 5 4
63 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
76 7 6 5 4
77 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
88 4 5 6 7
89 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
101 4 5 6 7
102 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
106 5. 如果只设置了QUIRK_LSW32_IS_FIRST，我们这样做：
110 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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/Documentation/networking/devlink/
Docteontx2.rst16 :widths: 5 5 5 85
32 :widths: 5 5 5 85
47 :widths: 5 5 5 85
Dmlxsw.rst24 :widths: 5 5 5 85
46 :widths: 5 5 90
67 :widths: 5 5 90
89 :widths: 5 5 90
/Documentation/input/devices/
Delantech.rst22 5. Hardware version 2
58 4 allows tracking up to 5 fingers.
183 bit 7 6 5 4 3 2 1 0
197 bit 7 6 5 4 3 2 1 0
240 bit 7 6 5 4 3 2 1 0
251 bit 7 6 5 4 3 2 1 0
259 bit 7 6 5 4 3 2 1 0
268 bit 7 6 5 4 3 2 1 0
289 bit 7 6 5 4 3 2 1 0
308 bit 7 6 5 4 3 2 1 0
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/Documentation/devicetree/bindings/iio/dac/
Dadi,ad5380.yaml20 - adi,ad5380-5
22 - adi,ad5381-5
24 - adi,ad5382-5
26 - adi,ad5383-5
28 - adi,ad5384-5
30 - adi,ad5390-5
32 - adi,ad5391-5
34 - adi,ad5392-5
59 compatible = "adi,ad5390-5";
/Documentation/devicetree/bindings/clock/
Didt,versaclock5.yaml7 title: IDT VersaClock 5 and 6 programmable I2C clock generators
10 The IDT VersaClock 5 and VersaClock 6 are programmable I2C
16 - 5P49V5923:
21 - 5P49V5933:
53 - idt,5p49v5923
54 - idt,5p49v5925
55 - idt,5p49v5933
56 - idt,5p49v5935
57 - idt,5p49v60
58 - idt,5p49v6901
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Drenesas,5p35023.yaml4 $id: http://devicetree.org/schemas/clock/renesas,5p35023.yaml#
7 title: Renesas 5p35023 VersaClock 3 programmable I2C clock generator
13 The 5P35023 is a VersaClock programmable clock generator and
15 express applications. The 5P35023 device is a three PLL
29 …https://www.renesas.com/us/en/products/clocks-timing/clock-generation/programmable-clocks/5p35023-…
34 - renesas,5p35023
42 0 - REF, 1 - SE1, 2 - SE2, 3 - SE3, 4 - DIFF1, 5 - DIFF2.
70 compatible = "renesas,5p35023";
77 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
84 <&versa3 4>, <&versa3 5>;
/Documentation/RCU/Design/Memory-Ordering/
DTreeRCU-hotplug.svg2 <!-- Creator: fig2dev Version 3.2 Patchlevel 5e -->
46 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
60 d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
74 d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
116 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
145 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
159 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
173 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
224 id="Arrow2Lend-5"
256 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
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DTreeRCU-dyntick.svg2 <!-- Creator: fig2dev Version 3.2 Patchlevel 5e -->
46 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
60 d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
74 d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
116 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
145 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
159 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
173 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
224 id="Arrow2Lend-5"
256 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
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DTreeRCU-gp-init-1.svg2 <!-- Creator: fig2dev Version 3.2 Patchlevel 5e -->
46 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
60 d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
74 d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
116 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
145 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
159 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
173 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
224 id="Arrow2Lend-5"
256 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
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DTreeRCU-gp-fqs.svg2 <!-- Creator: fig2dev Version 3.2 Patchlevel 5e -->
46 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
60 d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
74 d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
116 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
145 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
159 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
173 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
224 id="Arrow2Lend-5"
256 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
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/Documentation/devicetree/bindings/dma/
Drenesas,rcar-dmac.yaml62 - pattern: "^ch([0-9]|1[0-5])$"
63 - pattern: "^ch([0-9]|1[0-5])$"
64 - pattern: "^ch([0-9]|1[0-5])$"
65 - pattern: "^ch([0-9]|1[0-5])$"
66 - pattern: "^ch([0-9]|1[0-5])$"
67 - pattern: "^ch([0-9]|1[0-5])$"
68 - pattern: "^ch([0-9]|1[0-5])$"
69 - pattern: "^ch([0-9]|1[0-5])$"
70 - pattern: "^ch([0-9]|1[0-5])$"
71 - pattern: "^ch([0-9]|1[0-5])$"
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/Documentation/devicetree/bindings/nvmem/
Dmediatek,efuse.yaml64 bits = <0 5>;
68 bits = <5 5>;
76 bits = <0 5>;
80 bits = <5 5>;
88 bits = <0 5>;
92 bits = <5 5>;
/Documentation/admin-guide/perf/
Dhisi-pmu.rst52 $# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5
53 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5
61 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_core=0x3/ sleep 5
71 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_req=0x4/ sleep 5
75 3. Datasrc allows the user to check where the data comes from. It is 5 bits.
78 - 5'b00001: comes from L3C in this die;
79 - 5'b01000: comes from L3C in the cross-die;
80 - 5'b01001: comes from L3C which is in another socket;
81 - 5'b01110: comes from the local DDR;
82 - 5'b01111: comes from the cross-die DDR;
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/Documentation/core-api/
Dpacking.rst56 7 6 5 4
57 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
72 7 6 5 4
73 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
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99 4 5 6 7
100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
104 5. If just QUIRK_LSW32_IS_FIRST is set, we do it like this:
108 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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/Documentation/gpu/amdgpu/
Dapu-asic-info-table.csv9 Ryzen 7000 series (AM5), Raphael, 3.1.5, 10.3.6, 3.1.2, 5.2.6, 13.0.5
10 Ryzen 9000 series (AM5), Granite Ridge, 3.1.5, 10.3.6, 3.1.2, 5.2.6, 13.0.5
11 Ryzen 7x45 series (FL1), Dragon Range, 3.1.5, 10.3.6, 3.1.2, 5.2.6, 13.0.5
15 Ryzen AI 300 series, Strix Point, 3.5.0, 11.5.0, 4.0.5, 6.1.0, 14.0.0
/Documentation/devicetree/bindings/sound/
Dqcom,wcd937x-sdw.yaml34 WCD9370 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4
47 Supports maximum 5 rx soundwire ports.
53 WCD9370 RX Port 5 (DSD_L/R) <==> SWR1 Port 5 (DSD)
56 minItems: 5
57 maxItems: 5
59 enum: [1, 2, 3, 4, 5]
76 qcom,rx-port-mapping = <1 2 3 4 5>;
/Documentation/arch/x86/x86_64/
D5level-paging.rst4 5-level paging
14 5-level paging. It is a straight-forward extension of the current page
20 QEMU 2.9 and later support 5-level paging.
22 Virtual memory layout for 5-level paging is described in
26 Enabling 5-level paging
36 On x86, 5-level paging enables 56-bit userspace virtual address space.
39 information. It collides with valid pointers with 5-level paging and
56 Specifying high hint address on older kernel or on machine without 5-level
/Documentation/devicetree/bindings/net/wireless/
Dmarvell,sd8787.yaml42 marvell,caldata-txpwrlimit-5g-sub0:
44 description: Calibration data for sub-band 0 in the 5GHz band.
47 marvell,caldata-txpwrlimit-5g-sub1:
49 description: Calibration data for sub-band 1 in the 5GHz band.
52 marvell,caldata-txpwrlimit-5g-sub2:
54 description: Calibration data for sub-band 2 in the 5GHz band.
57 marvell,caldata-txpwrlimit-5g-sub3:
59 description: Calibration data for sub-band 3 in the 5GHz band.

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