Searched +full:50 +full:mhz (Results 1 – 25 of 62) sorted by relevance
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| /Documentation/devicetree/bindings/clock/ |
| D | armada3700-periph-clock.txt | 36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
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| D | starfive,jh7100-clkgen.yaml | 22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
24 - description: RMII reference clock (50 MHz)
25 - description: RGMII RX clock (125 MHz)
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| D | artpec6.txt | 11 - "sys_refclk": External 50 Mhz oscillator (required)
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| D | st,stm32mp25-rcc.yaml | 36 - description: CK_SCMI_HSE High Speed External oscillator (8 to 48 MHz)
37 - description: CK_SCMI_HSI High Speed Internal oscillator (~ 64 MHz)
38 - description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz)
93 - description: CK_SCMI_FLEXGEN_50 flexgen clock 50
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| D | st,nomadik.txt | 18 i.e. the driver output for the main (~19.2 MHz) chrystal,
91 50: HSICLKTX
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| /Documentation/scsi/ |
| D | aic7xxx.rst | 26 aic7770 10 EISA/VL 10MHz 16Bit 4 1
27 aic7850 10 PCI/32 10MHz 8Bit 3
28 aic7855 10 PCI/32 10MHz 8Bit 3
29 aic7856 10 PCI/32 10MHz 8Bit 3
30 aic7859 10 PCI/32 20MHz 8Bit 3
31 aic7860 10 PCI/32 20MHz 8Bit 3
32 aic7870 10 PCI/32 10MHz 16Bit 16
33 aic7880 10 PCI/32 20MHz 16Bit 16
34 aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8
35 aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 8
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| D | 53c700.rst | 61 53c700 25MHz
62 53c700-66 50MHz
63 53c710 40Mhz
106 Set to the clock speed of the chip in MHz.
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| /Documentation/fb/ |
| D | viafb.modes | 10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
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| D | s3fb.rst | 39 lower pixclocks (maximum usually between 50-60 MHz, depending on specific
40 hardware, i get best results from plain S3 Trio32 card - about 75 MHz). This
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| /Documentation/devicetree/bindings/net/ |
| D | micrel.txt | 23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
24 bit selects 25 MHz mode
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
27 than 50 MHz clock mode.
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| D | nxp,tja11xx.yaml | 54 typically derived from an external 25MHz crystal. Alternatively,
55 a 50MHz clock signal generated by an external oscillator can be
56 connected to pin REF_CLK. A third option is to connect a 25MHz
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| D | ti,dp83822.yaml | 87 - RMII master, where the PHY outputs a 50MHz reference clock which can
89 - RMII slave, where the PHY expects a 50MHz reference clock input
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| D | stm32-dwmac.yaml | 94 set this property in RMII mode when you have PHY without crystal 50MHz and want to
106 set this property in RMII mode when you have PHY without crystal 50MHz and want to
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| D | rockchip-dwmac.yaml | 79 For RGMII, it must be "input", means main clock(125MHz)
81 For RMII, "input" means PHY provides the reference clock(50MHz),
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| D | sti-dwmac.txt | 20 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
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| D | amlogic,g12a-mdio-mux.yaml | 31 - description: SoC 50MHz MPLL
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| /Documentation/devicetree/bindings/mtd/ |
| D | spear_smi.txt | 23 clock-rate = <50000000>; /* 50MHz */
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| /Documentation/devicetree/bindings/spi/ |
| D | jcore,spi.txt | 18 fixed 50 MHz.
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | sony,imx335.yaml | 32 description: Clock frequency from 6 to 27 MHz, 37.125MHz, 74.25MHz
97 reset-gpios = <&gpio 50 GPIO_ACTIVE_LOW>;
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| /Documentation/devicetree/bindings/mfd/ |
| D | st,stmpe.yaml | 79 0 = 1.625 MHz
80 1 = 3.25 MHz
81 2, 3 = 6.5 MHz
156 1 = 50 us
162 7 = 50 ms
175 6 = 50 ms
190 1 = 50 mA (typical 80 mA max)
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| /Documentation/admin-guide/media/ |
| D | vivid.rst | 344 supports frames per second settings of 10, 15, 25, 30, 50 and 60 fps. Which ones
367 visible. For 50 Hz standards the top field is the oldest and the bottom field
372 contain the top field for 50 Hz standards and the bottom field for 60 Hz
387 The TV 'tuner' supports a frequency range of 44-958 MHz. Channels are available
388 every 6 MHz, starting from 49.25 MHz. For each channel the generated image
389 will be in color for the +/- 0.25 MHz around it, and in grayscale for
390 +/- 1 MHz around the channel. Beyond that it is just noise. The VIDIOC_G_TUNER
391 ioctl will return 100% signal strength for +/- 0.25 MHz and 50% for +/- 1 MHz.
395 The audio subchannels that are returned are MONO for the +/- 1 MHz range around
396 a valid channel frequency. When the frequency is within +/- 0.25 MHz of the
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| /Documentation/devicetree/bindings/mmc/ |
| D | sdhci-st.txt | 41 - max-frequency: Can be 200MHz, 100MHz or 50MHz (default) and used for
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | intel,pinctrl-keembay.yaml | 78 0 - Fast(~100MHz)
79 1 - Slow(~50MHz)
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| /Documentation/i2c/busses/ |
| D | i2c-ocores.rst | 58 .clock_khz = 50000, /* input clock of 50MHz */
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| /Documentation/arch/arm/ |
| D | setup.rst | 101 0-66 MHz. If no params are passed or a value of zero is passed,
102 then a value of 50 Mhz is the default on 21285 architectures.
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