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/Documentation/input/devices/
Delantech.rst22 5. Hardware version 2
57 combine a status packet with multiple head or motion packets. Hardware version
58 4 allows tracking up to 5 fingers.
60 Some Hardware version 3 and version 4 also have a trackpoint which uses a
67 Note that a mouse button is also associated with either the touchpad or the
68 trackpoint when a trackpoint is available. Disabling the Touchpad in xorg
101 Currently a value of "1" will turn on some basic debugging and a value of
107 generate quite a lot of data!
118 calculating a parity bit for the last 3 bytes of each packet. The driver
175 By echoing a hexadecimal value to a register it contents can be altered.
[all …]
Dalps.rst8 ALPS touchpads, called versions 1, 2, 3, 4, 5, 6, 7 and 8.
11 integrated into a variety of laptops and netbooks. These new touchpads
23 (Compatibility ID) definition as a way to uniquely identify the
24 different ALPS variants but there did not appear to be a 1:1 mapping.
32 E8-E6-E6-E6-E9. An ALPS touchpad should respond with either 00-00-0A or
45 The new ALPS touchpads have an E7 signature of 73-03-50 or 73-03-0A but
51 Protocol versions 3 and 4 have a command mode that is used to read and write
52 one-byte device registers in a 16-bit address space. The command sequence
54 with 88-07 followed by a third byte. This third byte can be used to determine
59 While in command mode, register addresses can be set by first sending a
[all …]
/Documentation/admin-guide/perf/
Dhisi-pmu.rst26 Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
37 The driver also provides a "cpumask" sysfs attribute, which shows the CPU core
52 $# perf stat -a -e hisi_sccl3_l3c0/rd_hit_cpipe/ sleep 5
53 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02/ sleep 5
59 specified as a bitmap::
61 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_core=0x3/ sleep 5
71 $# perf stat -a -e hisi_sccl3_l3c0/config=0x02,tt_req=0x4/ sleep 5
75 3. Datasrc allows the user to check where the data comes from. It is 5 bits.
78 - 5'b00001: comes from L3C in this die;
79 - 5'b01000: comes from L3C in the cross-die;
[all …]
/Documentation/devicetree/bindings/clock/
Drenesas,5p35023.yaml4 $id: http://devicetree.org/schemas/clock/renesas,5p35023.yaml#
7 title: Renesas 5p35023 VersaClock 3 programmable I2C clock generator
13 The 5P35023 is a VersaClock programmable clock generator and
15 express applications. The 5P35023 device is a three PLL
23 The driver can read a full register map from the DT, and will use that
29 …https://www.renesas.com/us/en/products/clocks-timing/clock-generation/programmable-clocks/5p35023-…
34 - renesas,5p35023
42 0 - REF, 1 - SE1, 2 - SE2, 3 - SE3, 4 - DIFF1, 5 - DIFF2.
70 compatible = "renesas,5p35023";
77 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
[all …]
Dbrcm,iproc-clocks.yaml19 ASIU clocks are a special case. These clocks are derived directly from the
60 most iProc PLLs, this is an onboard crystal with a fixed rate.
109 crystal N/A N/A N/A
111 armpll crystal N/A N/A
122 audio_125 genpll 5 BCM_CYGNUS_GENPLL_AUDIO_125_CLK
130 smart_card lcpll0 5 BCM_CYGNUS_LCPLL0_SMART_CARD_CLK
138 ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED
159 crystal N/A N/A N/A
161 armpll crystal N/A N/A
180 crystal N/A N/A N/A
[all …]
/Documentation/core-api/
Dpacking.rst10 One can memory-map a pointer to a carefully crafted struct over the hardware
20 A more robust alternative to struct field definitions would be to extract the
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
37 into a CPU-usable number.
47 The following examples cover the memory layout of a packed u64 field.
56 7 6 5 4
57 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
72 7 6 5 4
73 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
[all …]
/Documentation/userspace-api/media/v4l/
Dmetafmt-vsp1-hgt.rst18 The VSP1 HGT is a histogram computation engine that operates on HSV
19 data. It operates on a possibly cropped and subsampled input image and
20 computes the sum, maximum and minimum of the S component as well as a
23 The histogram is a matrix of 6 Hue and 32 Saturation buckets, 192 in
24 total. Each HSV value is added to one or more buckets with a weight
33 The Hue position **m** (0 - 5) of the bucket in the matrix depends on
43 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5
50 5U 0L 0U 1L 1U 2L 2U 3L 3U 4L 4U 5L 5U 0L
61 Pixels with a hue value included in the centre of an area (between nL and nU
62 included) are attributed to that single area and given a weight of 16. Pixels
[all …]
Dpixfmt-rgb.rst9 These formats encode each pixel as a triplet of RGB values. They are packed
12 bits required to store a pixel is not aligned to a byte boundary, the data is
20 or a permutation thereof, collectively referred to as alpha formats) depend on
24 a meaningful value. Otherwise, when the device doesn't capture an alpha channel
25 but can set the alpha bit to a user-configurable value, the
28 the value specified by that control. Otherwise a corresponding format without
34 filled with meaningful values by applications. Otherwise a corresponding format
38 Formats that contain padding bits are named XRGB (or a permutation thereof).
44 - In all the tables that follow, bit 7 is the most significant bit in a byte.
46 respectively. 'a' denotes bits of the alpha component (if supported by the
[all …]
Dsubdev-formats.rst42 field on the source pad to request a specific colorspace for the media
57 this field on a source pad to request a specific Y'CbCr encoding
71 this field on a source pad to request a specific HSV encoding
87 this field on a source pad to request a specific quantization
101 this field on a source pad to request a specific transfer
156 While there is a relationship between image formats on buses and image
157 formats in memory (a raw Bayer image won't be magically converted to
162 transported over a serial bus, the media bus pixel code that describes a
163 parallel format that transfers a sample on a single clock cycle is used. For
167 MEDIA_BUS_FMT_BGR888_1X24. This is because there is effectively only a single
[all …]
/Documentation/networking/devlink/
Dmlxsw.rst24 :widths: 5 5 5 85
34 specified in milliseconds, with a minimum of ``3000``. The value of
46 :widths: 5 5 90
67 :widths: 5 5 90
89 :widths: 5 5 90
97 routed from a disabled router interface (RIF). This can happen during
103 routed through a disabled router interface (RIF). This can happen during
Dnetdevsim.rst24 :widths: 5 5 5 85
33 - Test parameter used to show how a driver-specific devlink parameter
41 The ``netdevsim`` driver exposes a ``dummy`` region as an example of how the
42 devlink-region interfaces work. A snapshot is taken whenever the
90 :widths: 5 5 90
97 - When a packet enters the device it is classified to a filtering
99 to trap packets for which a FID could not be found
/Documentation/devicetree/bindings/dma/
Dmoxa,moxart-dma.txt11 - #dma-cells : Should be 1, a single cell holding a line request number
26 described in the dma.txt file, using a two-cell specifier for each channel:
27 a phandle plus one integer cells.
30 1. A phandle pointing to the DMA controller.
35 For example, MMC request line is 5
40 interrupts = <5 0>;
42 dmas = <&dma 5>,
43 <&dma 5>;
/Documentation/devicetree/bindings/phy/
Dmicrochip,sparx5-serdes.yaml31 The SERDES6G is a high-speed SERDES interface, which can operate at
37 * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
41 The SERDES10G is a high-speed SERDES interface, which can operate at
47 * 5 Gbps (QSGMII/USGMII)
48 * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
54 The SERDES25G is a high-speed SERDES interface, which can operate at
59 * 5 Gbps (QSGMII/USGMII)
60 * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
67 pattern: "^serdes@[0-9a-f]+$"
/Documentation/userspace-api/media/rc/
Drc-protos.rst9 IR is encoded as a series of pulses and spaces, using a protocol. These
10 protocols can encode e.g. an address (which device should respond) and a
12 across different devices for a given protocol.
14 Therefore out the output of the IR decoder is a scancode; a single u32
17 Other things can be encoded too. Some IR protocols encode a toggle bit; this
22 Some remotes have a pointer-type device which can used to control the
29 rc-5 (RC_PROTO_RC5)
32 This IR protocol uses manchester encoding to encode 14 bits. There is a
41 * - rc-5 bit
65 * - 5
[all …]
/Documentation/admin-guide/acpi/
Dcppc_sysfs.rst12 CPPC defined in the ACPI spec describes a mechanism for the OS to manage the
13 performance of a logical processor on a contiguous and abstract performance
14 scale. CPPC exposes a set of registers to describe abstract performance scale,
30 -r--r--r-- 1 root root 65536 Mar 5 19:38 feedback_ctrs
31 -r--r--r-- 1 root root 65536 Mar 5 19:38 highest_perf
32 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_freq
33 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_nonlinear_perf
34 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_perf
35 -r--r--r-- 1 root root 65536 Mar 5 19:38 nominal_freq
36 -r--r--r-- 1 root root 65536 Mar 5 19:38 nominal_perf
[all …]
/Documentation/devicetree/bindings/net/
Dmicrel.txt14 KSZ8021: register 0x1f, bits 5..4
15 KSZ8031: register 0x1f, bits 5..4
16 KSZ8051: register 0x1f, bits 5..4
17 KSZ8081: register 0x1f, bits 5..4
18 KSZ8091: register 0x1f, bits 5..4
29 Note that this option in only needed for certain PHY revisions with a
31 Specifically, a clock reference ("rmii-ref" below) is always needed to
32 actually select a mode.
53 Some PHYs have a COMA mode input pin which puts the PHY into
55 to a GPIO of the SoC.
/Documentation/devicetree/bindings/input/touchscreen/
Dti,am3359-tsc.yaml17 description: Wires refer to application modes i.e. 4/5/8 wire touchscreen
20 enum: [4, 5, 8]
27 description: The sequencer supports a total of 16 programmable steps. Each
28 step is used to read a single coordinate. A single readout is enough but
29 multiple reads can increase the quality. A value of 5 means, 5 reads for
30 X, 5 for Y and 2 for Z (always). This utilises 12 of the 16 software steps
37 description: Different boards could have a different order for connecting
51 kept as low as possible, while avoiding false pen-up event. Start from a
54 so this does in fact function as a hardware knob for adjusting the amount
73 ti,coordinate-readouts = <5>;
/Documentation/hwmon/
Ducd9200.rst32 dedicated circuitry for DC/DC loop management with flash memory and a serial
35 This driver is a client driver to the core PMBus driver. Please see
73 in[2-5]_label "vout[1-4]".
74 in[2-5]_input Measured voltage. From READ_VOUT register.
75 in[2-5]_min Minimum Voltage. From VOUT_UV_WARN_LIMIT register.
76 in[2-5]_max Maximum voltage. From VOUT_OV_WARN_LIMIT register.
77 in[2-5]_lcrit Critical minimum Voltage. VOUT_UV_FAULT_LIMIT register.
78 in[2-5]_crit Critical maximum voltage. From VOUT_OV_FAULT_LIMIT
80 in[2-5]_min_alarm Voltage low alarm. From VOLTAGE_UV_WARNING status.
81 in[2-5]_max_alarm Voltage high alarm. From VOLTAGE_OV_WARNING status.
[all …]
Dtps546d24.rst22 The TPS546D24A is a highly integrated, non-isolated DC/DC converter capable
23 of high frequency operation and 40-A current output from a 7-mm x 5-mm
27 to provide up to 160 A on a single output. The device has an option to
28 overdrive the internal 5-V LDO with an external 5-V supply via the VDD5
/Documentation/devicetree/bindings/hwmon/
Dmoortec,mr75203.yaml13 A Moortec PVT (Process, Voltage, Temperature) monitoring logic design can
15 Such a design will usually consists of several Moortec's embedded analog IPs,
16 and a single Moortec controller (mr75203) to configure and control the IPs.
18 Some of the Moortec's analog hard IPs that can be used in a design:
29 TS, VM & PD also include a digital interface, which consists of configuration
58 PVT controller has 5 VM (voltage monitor) sensors.
59 vm-map defines CPU core to VM instance mapping. A
62 maxItems: 5
84 Defines the channels that use a mr76006 pre-scaler to divide the input
98 minimum: 5
[all …]
/Documentation/spi/
Dspi-lm70llp.rst16 This driver provides glue code connecting a National Semiconductor LM70 LLP
19 This is a SPI master controller driver. It can be used in conjunction with
20 (layered under) the LM70 logical driver (a "SPI protocol driver").
22 into a SPI bus with a single device, which will be driven by the generic
40 D1 3 --> V+ 5
41 D2 4 --> V+ 5
42 D3 5 --> V+ 5
43 D4 6 --> V+ 5
46 D7 9 --> SI/O 5
51 Note that since the LM70 uses a "3-wire" variant of SPI, the SI/SO pin
[all …]
/Documentation/admin-guide/device-mapper/
Ddm-raid.rst5 The device-mapper RAID (dm-raid) target provides a bridge from DM to MD.
6 It allows the MD RAID drivers to be accessed using a device-mapper
95 clear bits. A longer interval means less bitmap I/O but
96 resyncing after a failure is likely to take longer.
107 Stripe cache size (RAID 4/5/6 only)
115 a RAID10 configuration. The number of copies is can be
134 layout is what a traditional RAID10 would look like. The
135 3-device layout is what might be called a 'RAID1E - Integrated
175 value) to any reshape supporting raid levels 4/5/6 and 10.
176 RAID levels 4/5/6 allow for addition of devices (metadata
[all …]
/Documentation/driver-api/media/drivers/
Dsh_mobile_ceu_camera.rst26 +-5-- . -- -3-- -\
36 +-5'- .´ -/
49 Such a configuration can be produced by user requests:
51 S_CROP(left / top = (5) - (1), width / height = (5') - (5))
62 (5) to (5') - reverse sensor scale applied to CEU cropped width or height
63 (2) to (5) - reverse sensor scale applied to CEU cropped left or top
79 width_u = (5') - (5) = ((4') - (4)) * scale_s
91 5. Apply iterative sensor S_FMT for sensor output window.
105 left_ceu = (4)_new - (3)_new = ((5) - (2)) / scale_s_new
131 2. If smaller - iterate until a larger one is obtained. Result: sensor cropped
[all …]
/Documentation/arch/powerpc/
Dassociativity.rst7 of that domain. Resources subsets of a given domain that exhibit better
9 are represented as being members of a sub-grouping domain. This performance
17 Hypervisor indicates the type/form of associativity used via "ibm,architecture-vec-5 property".
18 Bit 0 of byte 5 in the "ibm,architecture-vec-5" property indicates usage of Form 0 or Form 1.
19 A value of 1 indicates the usage of Form 1 associativity. For Form 2 associativity
20 bit 2 of byte 5 in the "ibm,architecture-vec-5" property is used.
28 With Form 1 a combination of ibm,associativity-reference-points, and ibm,associativity
31 The “ibm,associativity” property contains a list of one or more numbers (domainID)
34 The “ibm,associativity-reference-points” property contains a list of one or more numbers
52 "ibm,associativity-reference-points" property, Form 2 allows a large number of primary domain
[all …]
/Documentation/arch/x86/x86_64/
D5level-paging.rst4 5-level paging
14 5-level paging. It is a straight-forward extension of the current page
20 QEMU 2.9 and later support 5-level paging.
22 Virtual memory layout for 5-level paging is described in
26 Enabling 5-level paging
36 On x86, 5-level paging enables 56-bit userspace virtual address space.
39 information. It collides with valid pointers with 5-level paging and
53 A high hint address would only affect the allocation in question, but not
56 Specifying high hint address on older kernel or on machine without 5-level

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