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/Documentation/userspace-api/media/dvb/
Dfe-bandwidth-t.rst30 - .. _BANDWIDTH-1-712-MHZ:
34 - 1.712 MHz
38 - .. _BANDWIDTH-5-MHZ:
42 - 5 MHz
44 - .. row 5
46 - .. _BANDWIDTH-6-MHZ:
50 - 6 MHz
54 - .. _BANDWIDTH-7-MHZ:
58 - 7 MHz
62 - .. _BANDWIDTH-8-MHZ:
[all …]
Dfe_property_parameters.rst63 typically 6MHz.
127 ATSC (version 1) No need to set. It is always 6MHz.
128 DMTB No need to set. It is always 8MHz.
129 DVB-T 6MHz, 7MHz and 8MHz.
130 DVB-T2 1.172 MHz, 5MHz, 6MHz, 7MHz, 8MHz and 10MHz
131 ISDB-T 5MHz, 6MHz, 7MHz and 8MHz, although most places
132 use 6MHz.
332 from position 1-8 to 5-13 or anything in between.
474 Possible values: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, -1 (AUTO)
542 - .. row 5
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/Documentation/devicetree/bindings/net/
Dmicrel.txt14 KSZ8021: register 0x1f, bits 5..4
15 KSZ8031: register 0x1f, bits 5..4
16 KSZ8051: register 0x1f, bits 5..4
17 KSZ8081: register 0x1f, bits 5..4
18 KSZ8091: register 0x1f, bits 5..4
23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
24 bit selects 25 MHz mode
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
27 than 50 MHz clock mode.
Dnxp,tja11xx.yaml54 typically derived from an external 25MHz crystal. Alternatively,
55 a 50MHz clock signal generated by an external oscillator can be
56 connected to pin REF_CLK. A third option is to connect a 25MHz
107 tja1102_phy1: ethernet-phy@5 {
/Documentation/fb/
Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
85 # 5 chars 1 lines
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
[all …]
Dmatroxfb.rst170 - 5 -> same as above
180 - 5 -> 2x1Mx32 SDRAM, 32MB
281 generated. If bit 5 (value 0x20) is set, sync on green is turned
294 maxclk:X maximum dotclock. X can be specified in MHz, kHz or Hz. Default is
327 - 83 MHz on G200
328 - 66 MHz on Millennium I
329 - 60 MHz on Millennium II
335 - my Millennium G200 oscillator has frequency range from 35 MHz to 380 MHz
336 (and it works with 8bpp on about 320 MHz dotclocks (and changed mclk)).
337 But Matrox says on product sheet that VCO limit is 50-250 MHz, so I believe
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/Documentation/scsi/
Ddc395x.rst45 0 20 Mhz
46 1 12.2 Mhz
47 2 10 Mhz
48 3 8 Mhz
49 4 6.7 Mhz
50 5 5.8 Hhz
51 6 5 Mhz
52 7 4 Mhz
68 5 0x20 32 Wide Negotiation
84 (*)5 0x20 32 Check for LUNs >= 1.
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Daic7xxx.rst26 aic7770 10 EISA/VL 10MHz 16Bit 4 1
27 aic7850 10 PCI/32 10MHz 8Bit 3
28 aic7855 10 PCI/32 10MHz 8Bit 3
29 aic7856 10 PCI/32 10MHz 8Bit 3
30 aic7859 10 PCI/32 20MHz 8Bit 3
31 aic7860 10 PCI/32 20MHz 8Bit 3
32 aic7870 10 PCI/32 10MHz 16Bit 16
33 aic7880 10 PCI/32 20MHz 16Bit 16
34 aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8
35 aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 8
[all …]
Daic79xx.rst16 5. Contacting Adaptec
28 AIC-7901A Single Channel 64-bit PCI-X 133MHz to
30 AIC-7901B Single Channel 64-bit PCI-X 133MHz to
32 AIC-7902A4 Dual Channel 64-bit PCI-X 133MHz to
34 AIC-7902B Dual Channel 64-bit PCI-X 133MHz to
41 Adaptec SCSI Card 39320 Dual Channel 64-bit PCI-X 133MHz to 7902A4/7902B
44 Adaptec SCSI Card 39320A Dual Channel 64-bit PCI-X 133MHz to 7902B
47 Adaptec SCSI Card 39320D Dual Channel 64-bit PCI-X 133MHz to 7902A4
50 Adaptec SCSI Card 39320D Dual Channel 64-bit PCI-X 133MHz to 7902A4
54 Adaptec SCSI Card 29320 Single Channel 64-bit PCI-X 133MHz to 7901A
[all …]
/Documentation/devicetree/bindings/clock/
Darmada3700-periph-clock.txt20 5 setm_tmx Serial Embedded Trace Module
36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
Dsamsung,exynosautov9-clock.yaml20 two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz).
48 maxItems: 5
52 maxItems: 5
71 - description: External reference clock (26 MHz)
87 - description: External reference clock (26 MHz)
105 - description: External reference clock (26 MHz)
123 - description: External reference clock (26 MHz)
141 - description: External reference clock (26 MHz)
161 - description: External reference clock (26 MHz)
183 - description: External reference clock (26 MHz)
[all …]
Dsamsung,exynos850-clock.yaml20 two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
50 maxItems: 5
54 maxItems: 5
73 - description: External reference clock (26 MHz)
89 - description: External reference clock (26 MHz)
107 - description: External reference clock (26 MHz)
125 - description: External reference clock (26 MHz)
143 - description: External reference clock (26 MHz)
167 - description: External reference clock (26 MHz)
187 - description: External reference clock (26 MHz)
[all …]
Dgoogle,gs101-clock.yaml16 is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
40 maxItems: 5
44 maxItems: 5
71 - description: External reference clock (24.576 MHz)
87 - description: External reference clock (24.576 MHz)
112 - description: External reference clock (24.576 MHz)
156 - description: External reference clock (24.576 MHz)
Dstarfive,jh7110-aoncrg.yaml22 - description: Main Oscillator (24 MHz)
29 - description: Main Oscillator (24 MHz)
37 - description: Main Oscillator (24 MHz)
47 - minItems: 5
Didt,versaclock5.yaml7 title: IDT VersaClock 5 and 6 programmable I2C clock generators
10 The IDT VersaClock 5 and VersaClock 6 are programmable I2C
16 - 5P49V5923:
21 - 5P49V5933:
53 - idt,5p49v5923
54 - idt,5p49v5925
55 - idt,5p49v5933
56 - idt,5p49v5935
57 - idt,5p49v60
58 - idt,5p49v6901
[all …]
/Documentation/admin-guide/pm/
Dintel-speed-select.rst152 enable-cpu-list:0,1,2,3,4,5,6,7,8,9,10,11,12,13,28,29,30,31,32,33,34,35,36,37,38,39,40,41
154 base-frequency(MHz):2600
168 condition is met, then base frequency of 2600 MHz can be maintained. To
181 enable-cpu-list:0,1,2,3,5,7,8,9,10,11,28,29,30,31,33,35,36,37,38,39
183 base-frequency(MHz):2800
211 This matches the base-frequency (MHz) field value displayed from the
261 Which shows that the base frequency now increased from 2600 MHz at performance
262 level 0 to 2800 MHz at performance level 4. As a result, any workload, which can
263 use fewer CPUs, can see a boost of 200 MHz compared to performance level 0.
424 Specify clos min in MHz with [--min|-n]
[all …]
/Documentation/devicetree/bindings/regulator/
Dmaxim,max8952.yaml42 enum: [0, 1, 2, 3, 4, 5, 6, 7]
51 - 5: 1mV/us
62 - 0: 26 MHz
63 - 1: 13 MHz
64 - 2: 19.2 MHz
65 Defaults to 26 MHz if not specified.
Dmps,mpq7920.yaml27 after their hardware counterparts BUCK[1-4], one LDORTC, and LDO[2-5]
36 1.1MHz, 1.65MHz, 2.2MHz, 2.75MHz
/Documentation/devicetree/bindings/input/
Diqs626a.yaml60 enum: [0, 1, 2, 3, 4, 5, 6, 7]
70 5: 135
84 enum: [0, 1, 2, 3, 4, 5, 6, 7]
94 5: Generic channel 1
271 1: 5 uA
283 0: 4 MHz (1 MHz)
284 1: 2 MHz (500 kHz)
285 2: 1 MHz (250 kHz)
397 0: 16 MHz (4 MHz)
398 1: 8 MHz (2 MHz)
[all …]
Diqs269a.yaml180 0: 16 MHz (4 MHz)
181 1: 8 MHz (2 MHz)
182 2: 4 MHz (1 MHz)
183 3: 2 MHz (500 kHz)
234 5: Slider 1 hold
330 default: [0, 1, 2, 3, 4, 5, 6, 7]
366 1: 5 uA
389 0: 4 MHz (1 MHz)
390 1: 2 MHz (500 kHz)
391 2: 1 MHz (250 kHz)
[all …]
/Documentation/admin-guide/acpi/
Dcppc_sysfs.rst30 -r--r--r-- 1 root root 65536 Mar 5 19:38 feedback_ctrs
31 -r--r--r-- 1 root root 65536 Mar 5 19:38 highest_perf
32 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_freq
33 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_nonlinear_perf
34 -r--r--r-- 1 root root 65536 Mar 5 19:38 lowest_perf
35 -r--r--r-- 1 root root 65536 Mar 5 19:38 nominal_freq
36 -r--r--r-- 1 root root 65536 Mar 5 19:38 nominal_perf
37 -r--r--r-- 1 root root 65536 Mar 5 19:38 reference_perf
38 -r--r--r-- 1 root root 65536 Mar 5 19:38 wraparound_time
47 * lowest_freq : CPU frequency corresponding to lowest_perf (in MHz).
[all …]
/Documentation/devicetree/bindings/cpu/
Dcpu-capacity.txt38 by the frequency (in MHz) at which the benchmark has been run, so that
39 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
55 mhz values (normalized w.r.t. the highest value found while parsing the DT).
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
128 capacity-dmips-mhz = <1024>;
139 capacity-dmips-mhz = <1024>;
[all …]
/Documentation/userspace-api/media/v4l/
Dvidioc-enumstd.rst137 rate, and PAL color modulation with a 4.43 MHz color subcarrier. Some
148 rate, and NTSC color modulation with a 4.43 MHz color subcarrier.
260 - 4433618.75 ± 5
262 (3582056.25 ± 5)
263 - :cspan:`3` 4433618.75 ± 5
268 * - Nominal radio-frequency channel bandwidth (MHz)
280 * - Sound carrier relative to vision carrier (MHz)
331 New Zealand uses a sound carrier displaced 5.4996 ± 0.0005 MHz from
337 is being introduced. The second carrier is 5.85 MHz above the vision
343 second sound carrier is 6.552 MHz above the vision carrier and is
[all …]
/Documentation/devicetree/bindings/clock/ti/davinci/
Dda8xx-cfgchip.txt18 This node provides two clocks. The clock at index 0 is the USB 2.0 PHY 48MHz
19 clock and the clock at index 1 is the USB 1.1 PHY 48MHz clock.
29 PLL DIV4.5 divider
43 - clock-names: shall be "pll0_sysclk3", "div4.5"
71 div4p5_clk: div4.5 {
81 clock-names = "pll0_sysclk3", "div4.5";
/Documentation/devicetree/bindings/mfd/
Dst,stmpe.yaml53 enum: [ 0, 1, 2, 3, 4, 5, 6 ]
61 5 = 96 clock ticks
79 0 = 1.625 MHz
80 1 = 3.25 MHz
81 2, 3 = 6.5 MHz
152 enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ]
160 5 = 5 ms
166 enum: [ 0, 1, 2, 3, 4, 5, 6, 7 ]
173 4 = 5 ms
174 5 = 10 ms
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