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/Documentation/userspace-api/media/v4l/
Dsubdev-formats.rst199 For instance, a format where pixels are encoded as 5-bits red, 5-bits
200 green and 5-bit blue values padded on the high bit, transferred as 2
260 - 5
617 - g\ :sub:`5`
662 - g\ :sub:`5`
769 - g\ :sub:`5`
806 - g\ :sub:`5`
913 - g\ :sub:`5`
935 - r\ :sub:`5`
941 - g\ :sub:`5`
[all …]
Dpixfmt-packed-hsv.rst14 The *saturation* (s) and the *value* (v) are measured in percentage of the
47 - 5
56 - 5
65 - 5
74 - 5
96 - h\ :sub:`5`
105 - s\ :sub:`5`
112 - v\ :sub:`7`
113 - v\ :sub:`6`
114 - v\ :sub:`5`
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Dconstraints.svg3 …><path id="path6263" transform="matrix(-.4 0 0 -.4 -4 0)" d="m0 0 5-5-17.5 5 17.5 5-5-5z" fill="#f…
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/Documentation/hwmon/
Dltc4245.rst52 in1_input 12v input voltage (mV)
53 in2_input 5v input voltage (mV)
54 in3_input 3v input voltage (mV)
55 in4_input Vee (-12v) input voltage (mV)
57 in1_min_alarm 12v input undervoltage alarm
58 in2_min_alarm 5v input undervoltage alarm
59 in3_min_alarm 3v input undervoltage alarm
60 in4_min_alarm Vee (-12v) input undervoltage alarm
62 curr1_input 12v current (mA)
63 curr2_input 5v current (mA)
[all …]
Ddme1737.rst66 up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and
70 Fan[3-6] and pwm[3,5-6] are optional features and their availability depends on
75 fan[4-6] and pwm[5-6] don't exist.
94 in0: +5VTR (+5V standby) 0V - 6.64V
95 in1: Vccp (processor core) 0V - 3V
96 in2: VCC (internal +3.3V) 0V - 4.38V
97 in3: +5V 0V - 6.64V
98 in4: +12V 0V - 16V
99 in5: VTR (+3.3V standby) 0V - 4.38V
100 in6: Vbat (+3.0V) 0V - 4.38V
[all …]
Dcorsair-psu.rst51 curr2_input Current on the 12v psu rail
52 curr2_crit Current max critical value on the 12v psu rail
53 curr3_input Current on the 5v psu rail
54 curr3_crit Current max critical value on the 5v psu rail
55 curr4_input Current on the 3.3v psu rail
56 curr4_crit Current max critical value on the 3.3v psu rail
59 in1_input Voltage of the 12v psu rail
60 in1_crit Voltage max critical value on the 12v psu rail
61 in1_lcrit Voltage min critical value on the 12v psu rail
62 in2_input Voltage of the 5v psu rail
[all …]
Dmc13783-adc.rst47 0 Battery Voltage (BATT) 2.50 - 4.65V -2.40V
49 2 Application Supply (BP) 2.50 - 4.65V -2.40V
50 3 Charger Voltage (CHRGRAW) 0 - 10V / /5
51 0 - 20V /10
52 4 Charger Current (CHRGISNSP-CHRGISNSN) -0.25 - 0.25V x4
53 5 General Purpose ADIN5 / Battery Pack Thermistor 0 - 2.30V No
54 6 General Purpose ADIN6 / Backup Voltage (LICELL) 0 - 2.30V / No /
55 1.50 - 3.50V -1.20V
56 7 General Purpose ADIN7 / UID / Die Temperature 0 - 2.30V / No /
57 0 - 2.55V / x0.9 / No
[all …]
Dfsp-3y.rst18 * in2_input 12V output voltage
19 * in3_input 5V output voltage
21 * curr2_input 12V output current
22 * curr3_input 5V output current
Dmax197.rst25 The A/D converters MAX197, and MAX199 are both 8-Channel, Multi-Range, 5V,
28 The available ranges for the MAX197 are {0,-5V} to 5V, and {0,-10V} to 10V,
29 while they are {0,-2V} to 2V, and {0,-4V} to 4V on the MAX199.
48 5 ACQMOD Internal or External Controlled Acquisition
Dmax127.rst23 a variety of ranges. The available ranges are {0,5V}, {0,10V}, {-5,5V}
24 and {-10,10V}.
Dmenf21bmc.rst41 in0_input +3.3V input voltage
42 in1_input +5.0V input voltage
43 in2_input +12.0V input voltage
44 in3_input +5V Standby input voltage
53 in3_label "5V_STANDBY"
Dadm1025.rst38 are provided, for monitoring +2.5V, +3.3V, +5V and +12V power supplies and
45 different manners. It can act as the +12V power-supply voltage analog
48 chip that way is obscure at least to me. The bit 5 of the configuration
52 properly, you'll have a wrong +12V reading or a wrong VID reading. The way
Dtps546d24.rst23 of high frequency operation and 40-A current output from a 7-mm x 5-mm
28 overdrive the internal 5-V LDO with an external 5-V supply via the VDD5
/Documentation/devicetree/bindings/iio/dac/
Dadi,ltc2664.yaml14 Analog Devices LTC2664 4 channel, 12-/16-Bit, +-10V DAC
31 v-pos-supply:
34 v-neg-supply:
61 0 - MPS2=GND, MPS1=GND, MSP0=GND (+-10V, reset to 0V)
62 1 - MPS2=GND, MPS1=GND, MSP0=VCC (+-5V, reset to 0V)
63 2 - MPS2=GND, MPS1=VCC, MSP0=GND (+-2.5V, reset to 0V)
64 3 - MPS2=GND, MPS1=VCC, MSP0=VCC (0V to 10, reset to 0V)
65 4 - MPS2=VCC, MPS1=GND, MSP0=GND (0V to 10V, reset to 5V)
66 5 - MPS2=VCC, MPS1=GND, MSP0=VCC (0V to 5V, reset to 0V)
67 6 - MPS2=VCC, MPS1=VCC, MSP0=GND (0V to 5V, reset to 2.5V)
[all …]
Dadi,ad3552r.yaml46 internal reference will be used. External reference must be 2.5V
49 description: Vref I/O driven by internal vref to 2.5V. If not set, Vref pin
147 Rfb1x for: 0 to 2.5 V; 0 to 3V; 0 to 5 V;
148 Rfb2x for: 0 to 10 V; -2.5 to 7.5V; -5 to 5 V;
179 Rfb1x for: 0 to 2.5 V; 0 to 5 V;
180 Rfb2x for: 0 to 10 V; -5 to 5 V;
181 Rfb4x for: -10 to 10V
233 adi,gain-offset = <5>;
/Documentation/devicetree/bindings/timer/
Driscv,timer.yaml7 title: RISC-V timer
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14 based on the time CSR defined by the RISC-V privileged specification. The
15 timer interrupts of this device are configured using the RISC-V SBI Time
16 extension or the RISC-V Sstc extension.
18 The clock frequency of RISC-V timer device is specified via the
47 interrupts-extended = <&cpu1intc 5>,
48 <&cpu2intc 5>,
49 <&cpu3intc 5>,
50 <&cpu4intc 5>;
/Documentation/devicetree/bindings/iio/adc/
Dti,ads1015.yaml62 5: Voltage over AIN1 and GND.
72 maximum: 5
75 0: +/- 6.144 V
76 1: +/- 4.096 V
77 2: +/- 2.048 V (default)
78 3: +/- 1.024 V
79 4: +/- 0.512 V
80 5: +/- 0.256 V
93 5: 2400
103 5: 250
[all …]
/Documentation/devicetree/bindings/sound/
Dti,pcm3168a.yaml44 description: Digital power supply regulator 1 (+3.3V)
47 description: Digital power supply regulator 2 (+3.3V)
50 description: ADC power supply regulator 1 (+5V)
53 description: ADC power supply regulator 2 (+5V)
56 description: DAC power supply regulator 1 (+5V)
59 description: DAC power supply regulator 2 (+5V)
Dcs35l32.txt25 3 = Boost voltage fixed at 5 V.
40 0 = 3.1V
41 1 = 3.2V
42 2 = 3.3V (Default)
43 3 = 3.4V
46 0 = 3.1V
47 1 = 3.2V
48 2 = 3.3V
49 3 = 3.4V (Default)
50 4 = 3.5V
[all …]
Dti,ts3a227e.yaml34 - 0 # 2.1 V
35 - 1 # 2.2 V
36 - 2 # 2.3 V
37 - 3 # 2.4 V
38 - 4 # 2.5 V
39 - 5 # 2.6 V
40 - 6 # 2.7 V
41 - 7 # 2.8 V
61 description: headset insertion debounce time in ms (datasheet section 9.6.5).
/Documentation/devicetree/bindings/media/cec/
Dcec-gpio.yaml17 Please note:: the maximum voltage for the CEC line is 3.63V, for the HPD and
18 5V lines it is 5.3V. So you may need some sort of level conversion
40 GPIO that the 5V line is connected to. Used for debugging changes on the
41 5V line.
/Documentation/userspace-api/media/dvb/
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/Documentation/userspace-api/media/cec/
Dcec-ioc-dqevent.rst170 - 5
185 * .. _`CEC-EVENT-PIN-5V-LOW`:
189 - Generated if the 5V pin goes from a high voltage to a low voltage.
191 capability set. When open() is called, the 5V pin can be read and
192 if the 5V is low, then an initial event will be generated for that
194 * .. _`CEC-EVENT-PIN-5V-HIGH`:
198 - Generated if the 5V pin goes from a low voltage to a high voltage.
200 capability set. When open() is called, the 5V pin can be read and
201 if the 5V is high, then an initial event will be generated for that
/Documentation/gpu/amdgpu/display/
Dglobal_sync_vblank.svg17 inkscape:version="0.92.5 (2060ec1f9f, 2020-04-08)"
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267 …d="M 15.875,27.125001 V 16.541666 H 26.458333 V 27.125001 H 177.27084 V 16.541666 h 10.58333 v 10.…
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/Documentation/spi/
Dspi-lm70llp.rst40 D1 3 --> V+ 5
41 D2 4 --> V+ 5
42 D3 5 --> V+ 5
43 D4 6 --> V+ 5
46 D7 9 --> SI/O 5

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