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/Documentation/fb/
Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
28 mode "640x480-60"
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
[all …]
Dmatroxfb.rst294 maxclk:X maximum dotclock. X can be specified in MHz, kHz or Hz. Default is
299 70 for modes derived from `vesa` with yres <= 400, 60Hz for
327 - 83 MHz on G200
328 - 66 MHz on Millennium I
329 - 60 MHz on Millennium II
335 - my Millennium G200 oscillator has frequency range from 35 MHz to 380 MHz
336 (and it works with 8bpp on about 320 MHz dotclocks (and changed mclk)).
337 But Matrox says on product sheet that VCO limit is 50-250 MHz, so I believe
364 It is time to redraw whole screen 1000 times in 1024x768, 60Hz. It is
369 faster, it is kernel-space only time on P-II/350 MHz, Millennium I in 33 MHz
[all …]
Ds3fb.rst39 lower pixclocks (maximum usually between 50-60 MHz, depending on specific
40 hardware, i get best results from plain S3 Trio32 card - about 75 MHz). This
Dintel810.rst23 - Intel 815 Internal graphics only, 100Mhz FSB
115 (default = 60/60)
119 using vsync1/vsync2 = 60/60, make sure hsync1/hsync2 has at least
200 better than 640x480 at 60Hz. HOWEVER, if your chipset/display combination
Duvesafb.rst123 (60 Hz).
142 maxclk:n Maximum pixel clock (in MHz).
164 Use the default refresh rate (60 Hz) if set to 1.
/Documentation/devicetree/bindings/mfd/
Domap-usb-host.txt40 * "usbhost_120m_fck" - 120MHz Functional clock.
43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
53 * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
54 * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
55 * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
56 * "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.
/Documentation/userspace-api/media/v4l/
Dvidioc-enumstd.rst136 ``V4L2_STD_PAL_60`` is a hybrid standard with 525 lines, 60 Hz refresh
137 rate, and PAL color modulation with a 4.43 MHz color subcarrier. Some
139 a 50/60 Hz agnostic PAL TV.
147 ``V4L2_STD_NTSC_443`` is a hybrid standard with 525 lines, 60 Hz refresh
148 rate, and NTSC color modulation with a 4.43 MHz color subcarrier.
268 * - Nominal radio-frequency channel bandwidth (MHz)
280 * - Sound carrier relative to vision carrier (MHz)
331 New Zealand uses a sound carrier displaced 5.4996 ± 0.0005 MHz from
337 is being introduced. The second carrier is 5.85 MHz above the vision
343 second sound carrier is 6.552 MHz above the vision carrier and is
[all …]
Dvidioc-g-dv-timings.rst116 - Pixel clock in Hz. Ex. 74.25MHz->74250000
264 1.001 speed to be compatible with 60 Hz based standards such as
317 60 vs 59.94 Hz, 30 vs 29.97 Hz or 24 vs 23.976 Hz.
/Documentation/devicetree/bindings/regulator/
Dmaxim,max8952.yaml62 - 0: 26 MHz
63 - 1: 13 MHz
64 - 2: 19.2 MHz
65 Defaults to 26 MHz if not specified.
91 pmic@60 {
/Documentation/devicetree/bindings/usb/
Ddwc3-xilinx.yaml39 - description: Master/Core clock, has to be >= 125 MHz
40 for SS operation and >= 60MHz for HS operation.
Dqcom,dwc3.yaml81 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
82 60MHz for HS operation.
87 mode. Its frequency should be 19.2MHz.
189 - description: Master/Core clock, has to be >= 125 MHz
190 for SS operation and >= 60MHz for HS operation.
/Documentation/devicetree/bindings/iio/adc/
Dadi,ad7192.yaml45 pin. If absent, internal 4.92MHz clock is used, which can be made
75 adi,rejection-60-Hz-enable:
77 This bit enables a notch at 60 Hz when the first notch of the sinc
79 60 Hz when the sinc filter first notch is at 50 Hz. This allows
80 simultaneous 50 Hz/ 60 Hz rejection.
204 adi,rejection-60-Hz-enable;
/Documentation/admin-guide/media/
Dvivid.rst334 framerate of 59.94 Hz is really different from 60 Hz. If the framerate
344 supports frames per second settings of 10, 15, 25, 30, 50 and 60 fps. Which ones
368 is the newest in time. For 60 Hz standards that is reversed: the bottom field
372 contain the top field for 50 Hz standards and the bottom field for 60 Hz
387 The TV 'tuner' supports a frequency range of 44-958 MHz. Channels are available
388 every 6 MHz, starting from 49.25 MHz. For each channel the generated image
389 will be in color for the +/- 0.25 MHz around it, and in grayscale for
390 +/- 1 MHz around the channel. Beyond that it is just noise. The VIDIOC_G_TUNER
391 ioctl will return 100% signal strength for +/- 0.25 MHz and 50% for +/- 1 MHz.
395 The audio subchannels that are returned are MONO for the +/- 1 MHz range around
[all …]
Dmgb4.rst187 | 0 - PLL < 50MHz (default)
188 | 1 - PLL >= 50MHz
236 The default frame rate limit is 60Hz.
/Documentation/devicetree/bindings/clock/
Dst,stm32mp25-rcc.yaml36 - description: CK_SCMI_HSE High Speed External oscillator (8 to 48 MHz)
37 - description: CK_SCMI_HSI High Speed Internal oscillator (~ 64 MHz)
38 - description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz)
103 - description: CK_SCMI_FLEXGEN_60 flexgen clock 60
Dst,nomadik.txt18 i.e. the driver output for the main (~19.2 MHz) chrystal,
101 60: MSPCLK3
Dsilabs,si5351.yaml205 clock-generator@60 {
212 /* Connect XTAL input to 25MHz reference */
228 * - Set initial clock frequency of 74.25MHz
/Documentation/devicetree/bindings/media/i2c/
Dovti,ov9282.yaml35 description: Clock frequency from 6 to 27MHz
85 camera@60 {
/Documentation/devicetree/bindings/memory-controllers/
Drockchip,rk3399-dmc.yaml108 Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
116 Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
124 Defines the auto PD disable frequency in MHz.
128 minimum: 1000000 # In case anyone thought this was MHz.
176 minimum: 1000000 # In case anyone thought this was MHz.
223 minimum: 1000000 # In case anyone thought this was MHz.
235 default: 60
283 default: 60
/Documentation/devicetree/bindings/input/
Diqs269a.yaml180 0: 16 MHz (4 MHz)
181 1: 8 MHz (2 MHz)
182 2: 4 MHz (1 MHz)
183 3: 2 MHz (500 kHz)
221 approximately 60-ms pulse to be asserted on the GPIO4 pin.
336 Decreases the internal measurement capacitance from 60 pF to 15 pF.
389 0: 4 MHz (1 MHz)
390 1: 2 MHz (500 kHz)
391 2: 1 MHz (250 kHz)
Diqs626a.yaml192 Decreases the internal measurement capacitance from 60 pF to 15 pF.
283 0: 4 MHz (1 MHz)
284 1: 2 MHz (500 kHz)
285 2: 1 MHz (250 kHz)
397 0: 16 MHz (4 MHz)
398 1: 8 MHz (2 MHz)
399 2: 4 MHz (1 MHz)
400 3: 2 MHz (500 kHz)
530 Decreases the internal measurement capacitance from 60 pF to 15 pF.
603 0: 4 MHz (1 MHz)
[all …]
/Documentation/devicetree/bindings/iio/amplifiers/
Dadi,hmc425a.yaml15 ADRF5750 2 dB LSB, 4-Bit, Silicon Digital Attenuator, 10 MHz to 60 GHz
/Documentation/watchdog/
Dwatchdog-parameters.rst44 Watchdog timeout in seconds. 1<= timeout <=63, default=60.
53 Watchdog timeout in seconds. (0 < timeout < 18000, default=60
74 Watchdog margin in seconds (default=60)
119 Watchdog margin in seconds (default 60s)
154 Watchdog heartbeat period in seconds from 1 to 600, default 60
160 Watchdog timeout in seconds. (1<=timeout<=15300, default=60)
196 Watchdog timeout in seconds. 1<= timeout <=131, default=60.
247 Watchdog timeout in seconds (default 60 s)
270 Watchdog margin in seconds (default 60)
286 Watchdog timeout in seconds, default=60
[all …]
/Documentation/devicetree/bindings/net/
Dstm32-dwmac.yaml94 set this property in RMII mode when you have PHY without crystal 50MHz and want to
106 set this property in RMII mode when you have PHY without crystal 50MHz and want to
205 clocks = <&rcc 62>, <&rcc 61>, <&rcc 60>;
/Documentation/driver-api/media/drivers/
Dradiotrack.rst32 broadcast TV channels, situated just below and above the 87.0-109.0 MHz range.
45 more or less limited from 87.0 to 109.0 MHz (the commercial FM broadcast
91 Results available by reading ioport >60 msec after last port write.

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