| /Documentation/devicetree/bindings/interconnect/ |
| D | mediatek,cci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jia-Wei Chang <jia-wei.chang@mediatek.com>
11 - Johnson Wang <johnson.wang@mediatek.com>
21 - mediatek,mt8183-cci
22 - mediatek,mt8186-cci
26 - description:
28 - description:
33 clock-names:
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| /Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-mediatek.txt | 5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp-v2.yaml
15 - proc-supply: Regulator for Vproc of CPU cluster.
18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
23 - mediatek,cci:
30 - #cooling-cells:
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| /Documentation/filesystems/ext4/ |
| D | blocks.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 ------
7 sectors between 1KiB and 64KiB, and the number of sectors must be an
11 page size (i.e. 64KiB blocks on a i386 which only has 4KiB memory
12 pages). By default a filesystem can contain 2^32 blocks; if the '64bit'
13 feature is enabled, then a filesystem can have 2^64 blocks. The location
17 For 32-bit filesystems, limits are as follows:
19 .. list-table::
21 :header-rows: 1
23 * - Item
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| /Documentation/devicetree/bindings/net/can/ |
| D | bosch,m_can.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Chandrasekar Ramakrishnan <rcsekar@samsung.com>
15 - $ref: can-controller.yaml#
23 - description: M_CAN registers map
24 - description: message RAM
26 reg-names:
28 - const: m_can
29 - const: message_ram
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| /Documentation/admin-guide/media/ |
| D | dvb_intro.rst | 1 .. SPDX-License-Identifier: GPL-2.0
12 structure of DVB-T cards are substantially similar to Analogue TV cards,
30 embedded within the modulated composite analogue signal -
38 signal encoded at a resolution of 768x576 24-bit color pixels over 25
39 frames per second - a fair amount of data is generated and must be
43 encoded and compressed form - similar to the form that is used in
46 The purpose of a simple budget digital TV card (DVB-T,C or S) is to
96 On this example, we're considering tuning into DVB-T channels in
115 The digital TV Scan utilities (like dvbv5-scan) have use a set of
116 compiled-in defaults for various countries and regions. Those are
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| /Documentation/devicetree/bindings/gpio/ |
| D | nuvoton,sgpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jim LIU <JJLIU0@nuvoton.com>
20 to 64 output pins, and up to 64 input pins, the pin is only for GPI or GPO.
22 - Support interrupt option for each input port and various interrupt
23 sensitivity options (level-high, level-low, edge-high, edge-low)
24 - ngpios is number of nuvoton,input-ngpios GPIO lines and nuvoton,output-ngpios GPIO lines.
25 nuvoton,input-ngpios GPIO lines is only for GPI.
26 nuvoton,output-ngpios GPIO lines is only for GPO.
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| /Documentation/arch/x86/x86_64/ |
| D | mm.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 Complete virtual memory map with 4-level page tables
12 - Negative addresses such as "-23 TB" are absolute addresses in bytes, counted down
13 from the top of the 64-bit address space. It's easier to understand the layout
14 when seen both in absolute addresses and in distance-from-top notation.
16 For example 0xffffe90000000000 == -23 TB, it's 23 TB lower than the top of the
17 64-bit address space (ffffffffffffffff).
22 - "16M TB" might look weird at first sight, but it's an easier way to visualize size
24 It also shows it nicely how incredibly large 64-bit address space is.
32 …0000000000000000 | 0 | 00007fffffffffff | 128 TB | user-space virtual memory, different …
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| /Documentation/admin-guide/cgroup-v1/ |
| D | hugetlb.rst | 7 # mount -t cgroup -o hugetlb none /sys/fs/cgroup
25 …rsvd.max_usage_in_bytes # show max "hugepagesize" hugetlb reservations and no-reserve faults
26 …hugetlb.<hugepagesize>.rsvd.usage_in_bytes # show current reservations and no-reserve f…
34 For a system supporting three hugepage sizes (64k, 32M and 1G), the control
46 hugetlb.64KB.limit_in_bytes
47 hugetlb.64KB.max_usage_in_bytes
48 hugetlb.64KB.numa_stat
49 hugetlb.64KB.usage_in_bytes
50 hugetlb.64KB.failcnt
51 hugetlb.64KB.rsvd.limit_in_bytes
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | nvidia,tegra20-ictlr.txt | 12 - compatible : should be: "nvidia,tegra<chip>-ictlr". The LIC on
13 subsequent SoCs remained backwards-compatible with Tegra30, so on
15 include "nvidia,tegra30-ictlr".
16 - reg : Specifies base physical address and size of the registers.
19 - interrupt-controller : Identifies the node as an interrupt controller.
20 - #interrupt-cells : Specifies the number of cells needed to encode an
25 - Because this HW ultimately routes interrupts to the GIC, the
27 - Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
32 ictlr: interrupt-controller@60004000 {
33 compatible = "nvidia,tegra20-ictlr", "nvidia,tegra-ictlr";
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| D | marvell,gicp.txt | 2 -----------------------
11 - compatible: Must be "marvell,ap806-gicp"
13 - reg: Must be the address and size of the GICP SPI registers
15 - marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
18 - msi-controller: indicates that this is an MSI controller
22 gicp_spi: gicp-spi@3f0040 {
23 compatible = "marvell,ap806-gicp";
25 marvell,spi-ranges = <64 64>, <288 64>;
26 msi-controller;
|
| /Documentation/devicetree/bindings/opp/ |
| D | opp-v2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 - $ref: opp-v2-base.yaml#
17 const: operating-points-v2
22 - |
24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
28 #address-cells = <1>;
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| D | allwinner,sun50i-h6-operating-points.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
20 - $ref: opp-v2-base.yaml#
25 - allwinner,sun50i-h6-operating-points
26 - allwinner,sun50i-h616-operating-points
28 nvmem-cells:
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| /Documentation/sound/cards/ |
| D | hdspm.rst | 2 Software Interface ALSA-DSP MADI Driver
5 (translated from German, so no good English ;-),
7 2004 - winfried ritsch
11 the Controls and startup-options are ALSA-Standard and only the
19 ------------------
21 * number of channels -- depends on transmission mode
29 * Single Speed -- 1..64 channels
34 all 64 channels are available for the mixer, so channel count
37 * Double Speed -- 1..32 channels
40 Note: Choosing the 56-channel mode for
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| /Documentation/admin-guide/auxdisplay/ |
| D | ks0108.rst | 7 :Date: 2006-10-27
19 ---------------------
25 ---------------------
30 :Webpage: -
31 :Device Webpage: -
33 :Width: 64
34 :Height: 64
37 :Addresses: 64 each page
39 :Memory size: 8 * 64 * 1 = 512 bytes
43 ---------
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|
| /Documentation/devicetree/bindings/gpu/ |
| D | arm,mali-midgard.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/gpu/arm,mali-midgard.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
14 pattern: '^gpu@[a-f0-9]+$'
17 - items:
18 - enum:
19 - samsung,exynos5250-mali
20 - const: arm,mali-t604
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| /Documentation/devicetree/bindings/display/msm/ |
| D | qcom,x1e80100-mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,x1e80100-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Abel Vesa <abel.vesa@linaro.org>
13 X1E80100 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,x1e80100-mdss
24 - description: Display AHB
25 - description: Display hf AXI
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|
| D | qcom,sm7150-mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm7150-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Danila Tikhonov <danila@jiaxyga.com>
13 SM7150 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm7150-mdss
24 - description: Display ahb clock from gcc
25 - description: Display hf axi clock
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|
| D | qcom,sm8450-dpu.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8450-dpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
12 $ref: /schemas/display/msm/dpu-common.yaml#
16 const: qcom,sm8450-dpu
20 - description: Address offset and size for mdp register set
21 - description: Address offset and size for vbif register set
23 reg-names:
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| D | qcom,sm7150-dpu.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm7150-dpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Danila Tikhonov <danila@jiaxyga.com>
12 $ref: /schemas/display/msm/dpu-common.yaml#
16 const: qcom,sm7150-dpu
20 - description: Address offset and size for mdp register set
21 - description: Address offset and size for vbif register set
23 reg-names:
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| D | qcom,sc7280-mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7280-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sc7280-mdss
25 - description: Display AHB clock from gcc
26 - description: Display AHB clock from dispcc
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| /Documentation/arch/powerpc/ |
| D | kaslr-booke32.rst | 1 .. SPDX-License-Identifier: GPL-2.0
14 map or copy kernel to a proper place and relocate. Freescale Book-E
22 pass entropy via the /chosen/kaslr-seed node in device tree.
25 image. The memory will be split in 64M zones. We will use the lower 8
26 bit of the entropy to decide the index of the 64M zone. Then we chose a
27 16K aligned offset inside the 64M zone to put the kernel in::
31 |--> 64M <--|
33 +---------------+ +----------------+---------------+
35 +---------------+ +----------------+---------------+
37 |-----> offset <-----|
|
| /Documentation/arch/arm64/ |
| D | asymmetric-32bit.rst | 2 Asymmetric 32-bit SoCs
7 This document describes the impact of asymmetric 32-bit SoCs on the
8 execution of 32-bit (``AArch32``) applications.
10 Date: 2021-05-17
16 of the CPUs are capable of executing 32-bit user applications. On such
19 ``execve(2)`` of 32-bit ELF binaries, with the latter returning
20 ``-ENOEXEC``. If the mismatch is detected during late onlining of a
21 64-bit-only CPU, then the onlining operation fails and the new CPU is
25 running legacy 32-bit binaries. Unsurprisingly, that doesn't work very
28 It seems inevitable that future SoCs will drop 32-bit support
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| /Documentation/scsi/ |
| D | aic7xxx.rst | 1 .. SPDX-License-Identifier: GPL-2.0
5 Adaptec Aic7xxx Fast -> Ultra160 Family Manager Set v7.0
35 aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 8
36 aic7892 20 PCI/64-66 80MHz 16Bit 16 3 4 5 6 7 8
40 aic7897 20 PCI/64 40MHz 16Bit 16 2 3 4 5 6 7 8
41 aic7899 20 PCI/64-66 80MHz 16Bit 16 2 3 4 5 6 7 8
44 1. Multiplexed Twin Channel Device - One controller servicing two
46 2. Multi-function Twin Channel Device - Two controllers on one chip.
47 3. Command Channel Secondary DMA Engine - Allows scatter gather list
49 4. 64 Byte SCB Support - Allows disconnected, untagged request table
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| /Documentation/arch/riscv/ |
| D | vm-layout.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Virtual Memory Layout on RISC-V Linux
10 This document describes the virtual memory layout used by the RISC-V Linux
13 RISC-V Linux Kernel 32bit
16 RISC-V Linux Kernel SV32
17 ------------------------
21 RISC-V Linux Kernel 64bit
24 The RISC-V privileged architecture document states that the 64bit addresses
25 "must have bits 63–48 all equal to bit 47, or else a page-fault exception will
28 the RISC-V Linux Kernel resides.
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| /Documentation/userspace-api/media/v4l/ |
| D | metafmt-vsp1-hgo.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgo:
9 Renesas R-Car VSP1 1-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1 1-D
20 computes the minimum, maximum and sum of all pixels as well as per-channel
25 additionally output the histogram with 64 or 256 bins, resulting in four
28 - In *64 bins normal mode*, the HGO operates on the three channels independently
29 to compute three 64-bins histograms. RGB, YCbCr and HSV image formats are
31 - In *64 bins maximum mode*, the HGO operates on the maximum of the (R, G, B)
32 channels to compute a single 64-bins histogram. Only the RGB image format is
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|