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/Documentation/arch/arm64/
Dasymmetric-32bit.rst2 Asymmetric 32-bit SoCs
7 This document describes the impact of asymmetric 32-bit SoCs on the
8 execution of 32-bit (``AArch32``) applications.
10 Date: 2021-05-17
16 of the CPUs are capable of executing 32-bit user applications. On such
19 ``execve(2)`` of 32-bit ELF binaries, with the latter returning
20 ``-ENOEXEC``. If the mismatch is detected during late onlining of a
21 64-bit-only CPU, then the onlining operation fails and the new CPU is
25 running legacy 32-bit binaries. Unsurprisingly, that doesn't work very
28 It seems inevitable that future SoCs will drop 32-bit support
[all …]
Dmemory.rst9 tables with a 4KB page size and up to 3 levels with a 64KB page size.
12 with the 4KB page configuration, allowing 39-bit (512GB) or 48-bit
14 64KB pages, only 2 levels of translation tables, allowing 42-bit (4TB)
18 only available when running with a 64KB page size and expands the
21 TTBRx selection is given by bit 55 of the virtual address. The
23 contains only user (non-global) mappings. The swapper_pg_dir address is
27 AArch64 Linux memory layout with 4KB pages + 4 levels (48-bit)::
30 -----------------------------------------------------------------------
44 AArch64 Linux memory layout with 64KB pages + 3 levels (52-bit with HW support)::
47 -----------------------------------------------------------------------
[all …]
/Documentation/devicetree/bindings/mmc/
Dsdhci.txt7 - sdhci-caps-mask: The sdhci capabilities register is incorrect. This 64bit
8 property corresponds to the bits in the sdhci capability register. If the bit
9 is on in the mask then the bit is incorrect in the register and should be
10 turned off, before applying sdhci-caps.
11 - sdhci-caps: The sdhci capabilities register is incorrect. This 64bit
13 bit is on in the property then the bit should be turned on.
/Documentation/bpf/
Dclassic_vs_extended.rst12 - Number of registers increase from 2 to 10:
15 new layout extends this to be 10 internal registers and a read-only frame
16 pointer. Since 64-bit CPUs are passing arguments to functions via registers
17 the number of args from eBPF program to in-kernel function is restricted
18 to 5 and one register is used to accept return value from an in-kernel
20 sparcv9/mips64 have 7 - 8 registers for arguments; x86_64 has 6 callee saved
25 64-bit architectures.
27 On 32-bit architectures JIT may map programs that use only 32-bit arithmetic
30 R0 - R5 are scratch registers and eBPF program needs spill/fill them if
33 call predefined in-kernel functions, though.
[all …]
/Documentation/devicetree/bindings/dma/stm32/
Dst,stm32-mdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-mdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
11 supporting 64 independent DMA channels with 256 HW requests.
13 described in the dma.txt file, using a five-cell specifier for each channel:
21 3. A 32bit mask specifying the DMA channel configuration
22 -bit 0-1: Source increment mode
26 -bit 2-3: Destination increment mode
[all …]
/Documentation/devicetree/bindings/net/can/
Dbosch,m_can.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 - Chandrasekar Ramakrishnan <rcsekar@samsung.com>
15 - $ref: can-controller.yaml#
23 - description: M_CAN registers map
24 - description: message RAM
26 reg-names:
28 - const: m_can
29 - const: message_ram
[all …]
/Documentation/devicetree/bindings/arm/
Dqcom,coresight-tpdm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/arm/qcom,coresight-tpdm.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Trace, Profiling and Diagnostics Monitor - TPDM
13 Basic Counts (BC), Tenure Counts (TC), Continuous Multi-Bit (CMB), and Discrete
14 Single Bit (DSB). It performs data collection in the data producing clock
22 - Mao Jinlong <quic_jinlmao@quicinc.com>
23 - Tao Zhang <quic_taozha@quicinc.com>
31 - qcom,coresight-tpdm
[all …]
/Documentation/bpf/standardization/
Dinstruction-set.rst27 BCP 14 `<https://www.rfc-editor.org/info/rfc2119>`_
28 `<https://www.rfc-editor.org/info/rfc8174>`_
38 -----
40 a type's signedness (`S`) and bit width (`N`), respectively.
51 .. table:: Meaning of bit-width notation
54 N Bit width
59 64 64 bits
63 For example, `u32` is a type whose valid values are all the 32-bit unsigned
64 numbers and `s16` is a type whose valid values are all the 16-bit signed
68 ---------
[all …]
/Documentation/driver-api/
Dioctl.rst18 the ioctl system call. While this can be any 32-bit number that uniquely
22 ``include/uapi/asm-generic/ioctl.h`` provides four macros for defining
36 An 8-bit number, often a character literal, specific to a subsystem
37 or driver, and listed in Documentation/userspace-api/ioctl/ioctl-number.rst
40 An 8-bit number identifying the specific command, unique for a give
45 encodes the ``sizeof(data_type)`` value in a 13-bit or 14-bit integer,
74 handler returns either -ENOTTY or -ENOIOCTLCMD, which also results in
75 -ENOTTY being returned from the system call. Some subsystems return
76 -ENOSYS or -EINVAL here for historic reasons, but this is wrong.
79 -ENOIOCTLCMD in order to use the fallback conversion into native
[all …]
/Documentation/filesystems/ext4/
Dblocks.rst1 .. SPDX-License-Identifier: GPL-2.0
4 ------
7 sectors between 1KiB and 64KiB, and the number of sectors must be an
11 page size (i.e. 64KiB blocks on a i386 which only has 4KiB memory
12 pages). By default a filesystem can contain 2^32 blocks; if the '64bit'
13 feature is enabled, then a filesystem can have 2^64 blocks. The location
17 For 32-bit filesystems, limits are as follows:
19 .. list-table::
21 :header-rows: 1
23 * - Item
[all …]
Dchecksums.rst1 .. SPDX-License-Identifier: GPL-2.0
4 ---------
10 structures did not have space to fit a full 32-bit checksum, so only the
11 lower 16 bits are stored. Enabling the 64bit feature increases the data
12 structure size so that full 32-bit checksums can be stored for many data
13 structures. However, existing 32-bit filesystems cannot be extended to
14 enable 64bit mode, at least not without the experimental resize2fs
18 ``tune2fs -O metadata_csum`` against the underlying device. If tune2fs
20 checksum, it will request that you run ``e2fsck -D`` to have the
30 .. list-table::
[all …]
/Documentation/arch/x86/x86_64/
Dmm.rst1 .. SPDX-License-Identifier: GPL-2.0
7 Complete virtual memory map with 4-level page tables
12 - Negative addresses such as "-23 TB" are absolute addresses in bytes, counted down
13 from the top of the 64-bit address space. It's easier to understand the layout
14 when seen both in absolute addresses and in distance-from-top notation.
16 For example 0xffffe90000000000 == -23 TB, it's 23 TB lower than the top of the
17 64-bit address space (ffffffffffffffff).
22 - "16M TB" might look weird at first sight, but it's an easier way to visualize size
24 It also shows it nicely how incredibly large 64-bit address space is.
32 …0000000000000000 | 0 | 00007fffffffffff | 128 TB | user-space virtual memory, different …
[all …]
D5level-paging.rst1 .. SPDX-License-Identifier: GPL-2.0
4 5-level paging
9 Original x86-64 was limited by 4-level paging to 256 TiB of virtual address
10 space and 64 TiB of physical address space. We are already bumping into
11 this limit: some vendors offer servers with 64 TiB of memory today.
14 5-level paging. It is a straight-forward extension of the current page
20 QEMU 2.9 and later support 5-level paging.
22 Virtual memory layout for 5-level paging is described in
26 Enabling 5-level paging
30 Kernel with CONFIG_X86_5LEVEL=y still able to boot on 4-level hardware.
[all …]
/Documentation/virt/kvm/devices/
Dxics.rst1 .. SPDX-License-Identifier: GPL-2.0
25 -EINVAL Value greater than KVM_MAX_VCPU_IDS.
26 -EFAULT Invalid user pointer for attr->addr.
27 -EBUSY A vcpu is already connected to the device.
32 sources, each identified by a 20-bit source number, and a set of
40 64 bits of state which can be read and written using the
41 KVM_GET_ONE_REG and KVM_SET_ONE_REG ioctls on the vcpu. The 64 bit
43 least-significant end of the word:
50 * Pending IPI (inter-processor interrupt) priority, 8 bits
60 Each source has 64 bits of state that can be read and written using
[all …]
/Documentation/arch/x86/
Dentry_64.rst1 .. SPDX-License-Identifier: GPL-2.0
16 for 64-bit, arch/x86/entry/entry_32.S for 32-bit and finally
17 arch/x86/entry/entry_64_compat.S which implements the 32-bit compatibility
18 syscall entry points and thus provides for 32-bit processes the
19 ability to execute syscalls when running on 64-bit kernels.
25 - system_call: syscall instruction from 64-bit code.
27 - entry_INT80_compat: int 0x80 from 32-bit or 64-bit code; compat syscall
30 - entry_INT80_compat, ia32_sysenter: syscall and sysenter from 32-bit
33 - interrupt: An array of entries. Every IDT vector that doesn't
36 magically-generated functions that make their way to common_interrupt()
[all …]
Dusb-legacy-support.rst2 .. SPDX-License-Identifier: GPL-2.0
27 3) If AMD64 64-bit mode is enabled, again system crashes often happen,
28 because the SMM BIOS isn't expecting the CPU to be in 64-bit mode. The
29 BIOS manufacturers only test with Windows, and Windows doesn't do 64-bit
38 compiled-in, too.
/Documentation/process/
Dadding-syscalls.rst9 :ref:`Documentation/process/submitting-patches.rst <submittingpatches>`.
13 ------------------------
18 kernel, there are other possibilities -- choose what fits best for your
21 - If the operations involved can be made to look like a filesystem-like
26 - If the new functionality involves operations where the kernel notifies
30 - However, operations that don't map to
31 :manpage:`read(2)`/:manpage:`write(2)`-like operations
35 - If you're just exposing runtime system information, a new node in sysfs
41 - If the operation is specific to a particular file or file descriptor, then
47 - If the operation is specific to a particular task or process, then an
[all …]
/Documentation/devicetree/bindings/timer/
Dti,keystone-timer.txt3 This document provides bindings for the 64-bit timer in the KeyStone
4 architecture devices. The timer can be configured as a general-purpose 64-bit
5 timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
9 It is global timer is a free running up-counter and can generate interrupt
17 - compatible : should be "ti,keystone-timer".
18 - reg : specifies base physical address and count of the registers.
19 - interrupts : interrupt generated by the timer.
20 - clocks : the clock feeding the timer clock.
25 compatible = "ti,keystone-timer";
Dti,da830-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/ti,da830-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kousik Sanagavarapu <five231003@gmail.com>
13 This is a 64-bit timer found on TI's DaVinci architecture devices. The timer
14 can be configured as a general-purpose 64-bit timer, dual general-purpose
15 32-bit timers. When configured as dual 32-bit timers, each half can operate
18 The timer is a free running up-counter and can generate interrupts when the
23 const: ti,da830-timer
[all …]
/Documentation/translations/it_IT/process/
Dadding-syscalls.rst1 .. include:: ../disclaimer-ita.rst
3 :Original: :ref:`Documentation/process/adding-syscalls.rst <addsyscalls>`
14 :ref:`Documentation/translations/it_IT/process/submitting-patches.rst <it_submittingpatches>`.
18 ------------------------------------
23 ovvio, esistono altre possibilità - scegliete quella che meglio si adatta alle
26 - Se le operazioni coinvolte possono rassomigliare a quelle di un filesystem,
32 - Se la nuova funzionalità prevede operazioni dove il kernel notifica
36 - Tuttavia, le operazioni che non si sposano bene con operazioni tipo
41 - Se dovete esporre solo delle informazioni sul sistema, un nuovo nodo in
48 - Se l'operazione è specifica ad un particolare file o descrittore, allora
[all …]
/Documentation/translations/sp_SP/process/
Dadding-syscalls.rst1 .. include:: ../disclaimer-sp.rst
3 :Original: :ref:`Documentation/process/adding-syscalls.rst <addsyscalls>`
13 :ref:`Documentation/process/submitting-patches.rst <submittingpatches>` que
17 -----------------------------------
22 tradicionales, existen otras posibilidades -- elija la que mejor se adecúe
25 - Si se puede hacer que la operación se parezca a un objeto filesystem,
31 - Si la nueva funcionalidad involucra operaciones donde el kernel
36 - Sin embargo, operaciones que no mapean a operaciones similares a
41 - Si sólo está exponiendo información del runtime, un nuevo nodo en sysfs
49 - Si la operación es específica a un archivo o descriptor de archivo
[all …]
/Documentation/devicetree/bindings/powerpc/opal/
Dpower-mgt.txt1 IBM Power-Management Bindings
6 node @power-mgt in the device-tree by the firmware.
9 ----------------
12 - name: The name of the idle state as defined by the firmware.
14 - flags: indicating some aspects of this idle states such as the
15 extent of state-loss, whether timebase is stopped on this
18 - exit-latency: The latency involved in transitioning the state of the
21 - target-residency: The minimum time that the CPU needs to reside in
22 this idle state in order to accrue power-savings
26 ----------------
[all …]
/Documentation/scsi/
Daic7xxx.rst1 .. SPDX-License-Identifier: GPL-2.0
5 Adaptec Aic7xxx Fast -> Ultra160 Family Manager Set v7.0
26 aic7770 10 EISA/VL 10MHz 16Bit 4 1
27 aic7850 10 PCI/32 10MHz 8Bit 3
28 aic7855 10 PCI/32 10MHz 8Bit 3
29 aic7856 10 PCI/32 10MHz 8Bit 3
30 aic7859 10 PCI/32 20MHz 8Bit 3
31 aic7860 10 PCI/32 20MHz 8Bit 3
32 aic7870 10 PCI/32 10MHz 16Bit 16
33 aic7880 10 PCI/32 20MHz 16Bit 16
[all …]
/Documentation/locking/
Drobust-futex-ABI.rst43 consisting of three words. Each word is 32 bits on 32 bit arch's, or 64
44 bits on 64 bit arch's, and local byte order. Each thread should have
47 If a thread is running in 32 bit compatibility mode on a 64 native arch
48 kernel, then it can actually have two such structures - one using 32 bit
49 words for 32 bit compatibility mode, and one using 64 bit words for 64
50 bit native mode. The kernel, if it is a 64 bit kernel supporting 32 bit
63 is always a 32 bit word, unlike the other words above. The 'lock
79 The 'lock word' is always 32 bits, and is intended to be the same 32 bit
89 the kernel will walk this list, mark any such locks with a bit
162 1) if bit 31 (0x80000000) is set in that word, then attempt a futex
[all …]
/Documentation/arch/mips/
Dbooting.rst1 .. SPDX-License-Identifier: GPL-2.0
4 ------------------------
11 Similar to the arch/arm case (b), a DT-aware bootloader is expected to
20 512MB of the physical address space (0x00000000 - 0x1fffffff),
21 aligned on a 64 bit boundary.
27 This convention is defined for 32-bit systems only, as there are not
28 currently any 64-bit BMIPS implementations.

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