Searched +full:64 +full:- +full:byte (Results 1 – 25 of 184) sorted by relevance
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| /Documentation/bpf/standardization/ |
| D | instruction-set.rst | 27 BCP 14 `<https://www.rfc-editor.org/info/rfc2119>`_
28 `<https://www.rfc-editor.org/info/rfc8174>`_
38 -----
51 .. table:: Meaning of bit-width notation
59 64 64 bits
63 For example, `u32` is a type whose valid values are all the 32-bit unsigned
64 numbers and `s16` is a type whose valid values are all the 16-bit signed
68 ---------
70 The following byteswap functions are direction-agnostic. That is,
74 * be16: Takes an unsigned 16-bit number and converts it between
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| /Documentation/arch/sparc/oradax/ |
| D | dax-hv-api.txt | 3 Publication date 2017-09-25 08:21
5 Extracted via "pdftotext -f 547 -l 572 -layout sun4v_20170925.pdf"
16 live-migration and other system management activities.
20 …high speed processoring of database-centric operations. The coprocessors may support one or more of
28 …e Completion Area and, unless execution order is specifically restricted through the use of serial-
45 …device node in the guest MD (Section 8.24.17, “Database Analytics Accelerators (DAX) virtual-device
51 36.1.1.1. "ORCL,sun4v-dax" Device Compatibility
54 • No-op/Sync
81 36.1.1.2. "ORCL,sun4v-dax-fc" Device Compatibility
82 … "ORCL,sun4v-dax-fc" is compatible with the "ORCL,sun4v-dax" interface, and includes additional CCB
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| /Documentation/ABI/testing/ |
| D | sysfs-driver-wacom | 4 Contact: linux-bluetooth@vger.kernel.org
14 Contact: linux-input@vger.kernel.org
25 Contact: linux-input@vger.kernel.org
35 Contact: linux-input@vger.kernel.org
44 Contact: linux-input@vger.kernel.org
54 Contact: linux-input@vger.kernel.org
63 Contact: linux-input@vger.kernel.org
70 Contact: linux-input@vger.kernel.org
72 When writing a 1024 byte raw image in Wacom Intuos 4
74 of the device. The image is a 64x32 pixel 4-bit gray image. The
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| D | debugfs-cxl | 4 Contact: linux-cxl@vger.kernel.org
8 the device for the specified address. The DPA must be 64-byte
9 aligned and the length of the injected poison is 64-bytes. If
18 device returns 'Inject Poison Limit Reached' an -EBUSY error
26 Contact: linux-cxl@vger.kernel.org
32 for 64 bytes starting at address. It is not an error to clear
34 device cannot clear poison from the address, -ENXIO is returned.
41 Contact: linux-cxl@vger.kernel.org
51 0x2000 CXL.cache Protocol Uncorrectable non-fatal
54 0x10000 CXL.mem Protocol Uncorrectable non-fatal
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| /Documentation/devicetree/bindings/dma/stm32/ |
| D | st,stm32-mdma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-mdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
11 supporting 64 independent DMA channels with 256 HW requests.
13 described in the dma.txt file, using a five-cell specifier for each channel:
22 -bit 0-1: Source increment mode
26 -bit 2-3: Destination increment mode
30 -bit 8-9: Source increment offset size
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| /Documentation/userspace-api/media/v4l/ |
| D | pixfmt-cnf4.rst | 1 .. -*- coding: utf-8; mode: rst -*-
3 .. _V4L2-PIX-FMT-CNF4:
15 confidence information in range 0-15 with 0 indicating that the sensor was
19 Every two consecutive pixels are packed into a single byte.
20 Bits 0-3 of byte n refer to confidence value of depth pixel 2*n,
21 bits 4-7 to confidence value of depth pixel 2*n+1.
23 **Bit-packed representation.**
25 .. flat-table::
26 :header-rows: 0
27 :stub-columns: 0
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| D | metafmt-vsp1-hgo.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgo:
9 Renesas R-Car VSP1 1-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1 1-D
20 computes the minimum, maximum and sum of all pixels as well as per-channel
25 additionally output the histogram with 64 or 256 bins, resulting in four
28 - In *64 bins normal mode*, the HGO operates on the three channels independently
29 to compute three 64-bins histograms. RGB, YCbCr and HSV image formats are
31 - In *64 bins maximum mode*, the HGO operates on the maximum of the (R, G, B)
32 channels to compute a single 64-bins histogram. Only the RGB image format is
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| D | pixfmt-packed-yuv.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _packed-yuv:
15 - In all the tables that follow, bit 7 is the most significant bit in a byte.
16 - 'Y', 'Cb' and 'Cr' denote bits of the luma, blue chroma (also known as
30 seen in a 16-bit word, which is then stored in memory in little endian byte
32 format stores a pixel in a 16-bit word [15:0] laid out at as [Y'\ :sub:`4-0`
33 Cb\ :sub:`5-0` Cr\ :sub:`4-0`], and stored in memory in two bytes,
34 [Cb\ :sub:`2-0` Cr\ :sub:`4-0`] followed by [Y'\ :sub:`4-0` Cb\ :sub:`5-3`].
44 .. flat-table:: Packed YUV 4:4:4 Image Formats (less than 8bpc)
45 :header-rows: 2
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| /Documentation/bpf/ |
| D | classic_vs_extended.rst | 12 - Number of registers increase from 2 to 10:
15 new layout extends this to be 10 internal registers and a read-only frame
16 pointer. Since 64-bit CPUs are passing arguments to functions via registers
17 the number of args from eBPF program to in-kernel function is restricted
18 to 5 and one register is used to accept return value from an in-kernel
20 sparcv9/mips64 have 7 - 8 registers for arguments; x86_64 has 6 callee saved
25 64-bit architectures.
27 On 32-bit architectures JIT may map programs that use only 32-bit arithmetic
30 R0 - R5 are scratch registers and eBPF program needs spill/fill them if
33 call predefined in-kernel functions, though.
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| /Documentation/admin-guide/auxdisplay/ |
| D | ks0108.rst | 7 :Date: 2006-10-27
19 ---------------------
25 ---------------------
30 :Webpage: -
31 :Device Webpage: -
33 :Width: 64
34 :Height: 64
37 :Addresses: 64 each page
38 :Data size: 1 byte each address
39 :Memory size: 8 * 64 * 1 = 512 bytes
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| /Documentation/devicetree/bindings/eeprom/ |
| D | at25.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christian Eggers <ceggers@arri.de>
15 - pattern: "^eeprom@[0-9a-f]{1,2}$"
16 - pattern: "^fram@[0-9a-f]{1,2}$"
26 - items:
27 - enum:
28 - anvo,anv32e61w
29 - atmel,at25256B
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| /Documentation/virt/kvm/x86/ |
| D | msr.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 KVM-specific MSRs
16 ---------------
24 4-byte alignment physical address of a memory area which must be
42 An odd version indicates an in-progress update.
53 Note that although MSRs are per-CPU entities, the effect of this
63 4-byte aligned physical address of a memory area which must be in
80 updates of this structure is arbitrary and implementation-dependent.
89 An odd version indicates an in-progress update.
104 tsc-related quantity to nanoseconds
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| /Documentation/virt/kvm/devices/ |
| D | mpic.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 - KVM_DEV_TYPE_FSL_MPIC_20 Freescale MPIC v2.0
10 - KVM_DEV_TYPE_FSL_MPIC_42 Freescale MPIC v4.2
20 KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit)
25 KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit)
27 "attr" is the byte offset into the MPIC register space. Accesses
28 must be 4-byte aligned.
33 KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit)
37 For edge-triggered interrupts: Writing 1 is considered an activating
42 byte offset of the relevant IVPR from EIVPR0, divided by 32.
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| /Documentation/input/devices/ |
| D | alps.rst | 1 ----------------------
3 ----------------------
6 ------------
10 Since roughly mid-2010 several new ALPS touchpads have been released and
14 adequate. The design choices were to re-define the alps_model_data
29 ---------
32 E8-E6-E6-E6-E9. An ALPS touchpad should respond with either 00-00-0A or
33 00-00-64 if no buttons are pressed. The bits 0-2 of the first byte will be 1s
37 report" sequence: E8-E7-E7-E7-E9. The response is the model signature and is
41 model signature is always 73-02-64. To differentiate between these
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| D | iforce-protocol.rst | 7 Home page at `<http://web.archive.org/web/*/http://www.esil.univ-mrs.fr>`_
16 specify force effects to I-Force 2.0 devices. None of this information comes
25 send data to your I-Force device based on what you read in this document.
30 All values are hexadecimal with big-endian encoding (msb on the left). Beware,
31 values inside packets are encoded using little-endian. Bytes whose roles are
35 ------------------------
64 00 X-Axis lsb
65 01 X-Axis msb
66 02 Y-Axis lsb, or gas pedal for a wheel
67 03 Y-Axis msb, or brake pedal for a wheel
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| /Documentation/devicetree/bindings/mtd/ |
| D | gpio-control-nand.txt | 8 - compatible : "gpio-control-nand"
9 - reg : should specify localbus chip select and size used for the chip. The
12 - #address-cells, #size-cells : Must be present if the device has sub-nodes
14 - gpios : Specifies the GPIO pins to control the NAND device. The order of
18 - bank-width : Width (in bytes) of the device. If not present, the width
19 defaults to 1 byte.
20 - chip-delay : chip dependent delay for transferring data from array to
22 - gpio-control-nand,io-sync-reg : A 64-bit physical address for a read
25 GPIO state and before and after command byte writes, this register will be
28 The device tree may optionally contain sub-nodes describing partitions of the
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| /Documentation/crypto/ |
| D | descore-readme.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 ------------------------------------------------------------------------------
15 des - fast & portable DES encryption & decryption.
42 2. PORTABILITY to any byte-addressable host with a 32bit unsigned C type
43 3. Plug-compatible replacement for KERBEROS's low-level routines.
46 register-starved machines. My discussions with Richard Outerbridge,
51 up in a parameterized fashion so it can easily be modified by speed-daemon
58 compile on a SPARCStation 1 (cc -O4, gcc -O2):
60 this code (byte-order independent):
62 - 30us per encryption (options: 64k tables, no IP/FP)
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| /Documentation/arch/x86/x86_64/ |
| D | fsgs.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 notation is used to address a byte within a segment:
10 Segment-register:Byte-address
12 The segment base address is added to the Byte-address to compute the
14 instances of data with the identical Byte-address, i.e. the same code. The
15 selection of a particular instance is purely based on the base-address in
18 In 32-bit mode the CPU provides 6 segments, which also support segment
21 In 64-bit mode the CS/SS/DS/ES segments are ignored and the base address is
22 always 0 to provide a full 64bit address space. The FS and GS segments are
23 still functional in 64-bit mode.
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| /Documentation/networking/device_drivers/cellular/qualcomm/ |
| D | rmnet.rst | 1 .. SPDX-License-Identifier: GPL-2.0
24 sending aggregated bunch of MAP frames. rmnet driver will de-aggregate
36 Bit 0 1 2-7 8-15 16-31
39 Bit 32-x
49 ensure 4 byte alignment.
62 Bit 0 1 2-7 8-15 16-31
65 Bit 32-(x-33) (x-32)-x
75 ensure 4 byte alignment.
87 Bit 0-14 15 16-31
90 Bit 31-47 48-64
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| /Documentation/devicetree/bindings/display/msm/ |
| D | qcom,sm8650-mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8650-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neil Armstrong <neil.armstrong@linaro.org>
13 SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm8650-mdss
24 - description: Display AHB
25 - description: Display hf AXI
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| D | qcom,sm8450-mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8450-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
13 SM8450 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm8450-mdss
24 - description: Display AHB
25 - description: Display hf AXI
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| D | qcom,sm7150-mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm7150-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Danila Tikhonov <danila@jiaxyga.com>
13 SM7150 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm7150-mdss
24 - description: Display ahb clock from gcc
25 - description: Display hf axi clock
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| D | qcom,sm8150-mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8150-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
22 - const: qcom,sm8150-mdss
26 - description: Display AHB clock from gcc
27 - description: Display hf axi clock
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| /Documentation/scsi/ |
| D | arcmsr_spec.rst | 11 ------------
13 - InitThread message and return code
15 2. Doorbell is used for RS-232 emulation
16 ----------------------------------------
35 ---------------------
46 4. RS-232 emulation
47 -------------------
49 Currently 128 byte buffer is used:
52 1st uint32_t Data length (1--124)
53 Byte 4--127 Max 124 bytes of data
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| /Documentation/networking/ |
| D | oa-tc6-framework.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
4 OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface (TC6) Framework Support
8 ------------
11 single pair of conductors. The 10BASE-T1L (Clause 146) is a long reach
12 PHY supporting full duplex point-to-point operation over 1 km of single
13 balanced pair of conductors. The 10BASE-T1S (Clause 147) is a short reach
14 PHY supporting full / half duplex point-to-point operation over 15 m of
21 works in conjunction with the 10BASE-T1S PHY operating in multidrop mode.
23 The aforementioned PHYs are intended to cover the low-speed / low-cost
29 The MAC-PHY solution integrates an IEEE Clause 4 MAC and a 10BASE-T1x PHY
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