Searched +full:64 +full:bit (Results 1 – 25 of 471) sorted by relevance
12345678910>>...19
| /Documentation/arch/arm64/ |
| D | asymmetric-32bit.rst | 2 Asymmetric 32-bit SoCs
7 This document describes the impact of asymmetric 32-bit SoCs on the
8 execution of 32-bit (``AArch32``) applications.
16 of the CPUs are capable of executing 32-bit user applications. On such
19 ``execve(2)`` of 32-bit ELF binaries, with the latter returning
21 64-bit-only CPU, then the onlining operation fails and the new CPU is
25 running legacy 32-bit binaries. Unsurprisingly, that doesn't work very
28 It seems inevitable that future SoCs will drop 32-bit support
30 run 32-bit code on one of these transitionary platforms then you would
38 allowing 32-bit tasks to run on an asymmetric 32-bit system requires an
[all …]
|
| D | memory.rst | 9 tables with a 4KB page size and up to 3 levels with a 64KB page size.
12 with the 4KB page configuration, allowing 39-bit (512GB) or 48-bit
14 64KB pages, only 2 levels of translation tables, allowing 42-bit (4TB)
18 only available when running with a 64KB page size and expands the
21 TTBRx selection is given by bit 55 of the virtual address. The
27 AArch64 Linux memory layout with 4KB pages + 4 levels (48-bit)::
44 AArch64 Linux memory layout with 64KB pages + 3 levels (52-bit with HW support)::
76 Translation table lookup with 64KB pages::
86 | +-------------------------------> [47:42] L1 index (48-bit)
87 | [51:42] L1 index (52-bit)
[all …]
|
| /Documentation/devicetree/bindings/mmc/ |
| D | sdhci.txt | 7 - sdhci-caps-mask: The sdhci capabilities register is incorrect. This 64bit
8 property corresponds to the bits in the sdhci capability register. If the bit
9 is on in the mask then the bit is incorrect in the register and should be
11 - sdhci-caps: The sdhci capabilities register is incorrect. This 64bit
13 bit is on in the property then the bit should be turned on.
|
| /Documentation/bpf/ |
| D | classic_vs_extended.rst | 16 pointer. Since 64-bit CPUs are passing arguments to functions via registers
25 64-bit architectures.
27 On 32-bit architectures JIT may map programs that use only 32-bit arithmetic
35 - Register width increases from 32-bit to 64-bit:
37 Still, the semantics of the original 32-bit ALU operations are preserved
38 via 32-bit subregisters. All eBPF registers are 64-bit with 32-bit lower
39 subregisters that zero-extend into 64-bit if they are being written to.
43 32-bit architectures run 64-bit eBPF programs via interpreter.
44 Their JITs may convert BPF programs that only use 32-bit subregisters into
47 Operation is 64-bit, because on 64-bit architectures, pointers are also
[all …]
|
| /Documentation/devicetree/bindings/dma/stm32/ |
| D | st,stm32-mdma.yaml | 11 supporting 64 independent DMA channels with 256 HW requests.
21 3. A 32bit mask specifying the DMA channel configuration
22 -bit 0-1: Source increment mode
26 -bit 2-3: Destination increment mode
30 -bit 8-9: Source increment offset size
31 0x0: byte (8bit)
32 0x1: half-word (16bit)
33 0x2: word (32bit)
34 0x3: double-word (64bit)
35 -bit 10-11: Destination increment offset size
[all …]
|
| /Documentation/devicetree/bindings/net/can/ |
| D | bosch,m_can.yaml | 70 11-bit Filter 0-128 elements / 0-128 words
71 29-bit Filter 0-64 elements / 0-128 words
72 Rx FIFO 0 0-64 elements / 0-1152 words
73 Rx FIFO 1 0-64 elements / 0-1152 words
74 Rx Buffers 0-64 elements / 0-1152 words
75 Tx Event FIFO 0-32 elements / 0-64 words
86 - description: 11-bit Filter 0-128 elements / 0-128 words
89 - description: 29-bit Filter 0-64 elements / 0-128 words
91 maximum: 64
92 - description: Rx FIFO 0 0-64 elements / 0-1152 words
[all …]
|
| /Documentation/devicetree/bindings/arm/ |
| D | qcom,coresight-tpdm.yaml | 13 Basic Counts (BC), Tenure Counts (TC), Continuous Multi-Bit (CMB), and Discrete
14 Single Bit (DSB). It performs data collection in the data producing clock
48 Specifies the DSB(Discrete Single Bit) element size supported by
50 is enabled. DSB element size currently only supports 32-bit and 64-bit.
51 enum: [32, 64]
55 Specifies the CMB(Continuous Multi-Bit) element size supported by
57 is enabled. CMB element size currently only supports 8-bit, 32-bit
58 and 64-bit.
59 enum: [8, 32, 64]
63 Specifies the number of DSB(Discrete Single Bit) MSR(mux select register)
[all …]
|
| /Documentation/bpf/standardization/ |
| D | instruction-set.rst | 40 a type's signedness (`S`) and bit width (`N`), respectively.
51 .. table:: Meaning of bit-width notation
54 N Bit width
59 64 64 bits
63 For example, `u32` is a type whose valid values are all the 32-bit unsigned
64 numbers and `s16` is a type whose valid values are all the 16-bit signed
74 * be16: Takes an unsigned 16-bit number and converts it between
77 * be32: Takes an unsigned 32-bit number and converts it between
79 * be64: Takes an unsigned 64-bit number and converts it between
81 * bswap16: Takes an unsigned 16-bit number in either big- or little-endian
[all …]
|
| /Documentation/driver-api/ |
| D | ioctl.rst | 18 the ioctl system call. While this can be any 32-bit number that uniquely
36 An 8-bit number, often a character literal, specific to a subsystem
40 An 8-bit number identifying the specific command, unique for a give
45 encodes the ``sizeof(data_type)`` value in a 13-bit or 14-bit integer,
90 move to 64-bit time_t.
101 requires an expensive 64-bit division, a simple __u64 nanosecond value
112 32-bit compat mode
115 In order to support 32-bit user space running on a 64-bit machine, each
126 On the s390 architecture, 31-bit user space has ambiguous representations
127 for data pointers, with the upper bit being ignored. When running such
[all …]
|
| /Documentation/filesystems/ext4/ |
| D | blocks.rst | 7 sectors between 1KiB and 64KiB, and the number of sectors must be an
11 page size (i.e. 64KiB blocks on a i386 which only has 4KiB memory
12 pages). By default a filesystem can contain 2^32 blocks; if the '64bit'
13 feature is enabled, then a filesystem can have 2^64 blocks. The location
17 For 32-bit filesystems, limits are as follows:
27 - 64KiB
79 For 64-bit filesystems, limits are as follows:
89 - 64KiB
91 - 2^64
92 - 2^64
[all …]
|
| D | checksums.rst | 10 structures did not have space to fit a full 32-bit checksum, so only the
11 lower 16 bits are stored. Enabling the 64bit feature increases the data
12 structure size so that full 32-bit checksums can be stored for many data
13 structures. However, existing 32-bit filesystems cannot be extended to
14 enable 64bit mode, at least not without the experimental resize2fs
63 and truncated if the group descriptor size is 32 bytes (i.e. ^64bit)
|
| /Documentation/arch/x86/x86_64/ |
| D | mm.rst | 13 from the top of the 64-bit address space. It's easier to understand the layout
17 64-bit address space (ffffffffffffffff).
24 It also shows it nicely how incredibly large 64-bit address space is.
35 …0000800000000000 | +128 TB | ffff7fffffffffff | ~16M TB | ... huge, almost 64 bits wide hole of…
45 …ffff888000000000 | -119.5 TB | ffffc87fffffffff | 64 TB | direct mapping of all physical memory…
54 … | Identical layout to the 56-bit one from here on:
63 ffffffef00000000 | -68 GB | fffffffeffffffff | 64 GB | EFI region mapping space
80 - With 56-bit addresses, user-space memory gets expanded by a factor of 512x,
81 from 0.125 PB to 64 PB. All kernel mappings shift down to the -64 PB starting
91 …0000000000000000 | 0 | 00ffffffffffffff | 64 PB | user-space virtual memory, different …
[all …]
|
| D | 5level-paging.rst | 9 Original x86-64 was limited by 4-level paging to 256 TiB of virtual address
10 space and 64 TiB of physical address space. We are already bumping into
11 this limit: some vendors offer servers with 64 TiB of memory today.
36 On x86, 5-level paging enables 56-bit userspace virtual address space.
43 above 47-bit by default.
48 If hint address set above 47-bit, but MAP_FIXED is not specified, we try
51 from 47-bit window.
58 to allocation from 47-bit address space.
65 MPX (without MAWA extension) cannot handle addresses above 47-bit, so we
|
| /Documentation/virt/kvm/devices/ |
| D | xics.rst | 32 sources, each identified by a 20-bit source number, and a set of
40 64 bits of state which can be read and written using the
41 KVM_GET_ONE_REG and KVM_SET_ONE_REG ioctls on the vcpu. The 64 bit
60 Each source has 64 bits of state that can be read and written using
63 the interrupt source number. The 64 bit state word has the following
77 * Level sensitive flag, 1 bit
79 This bit is 1 for a level-sensitive interrupt source, or 0 for
82 * Masked flag, 1 bit
84 This bit is set to 1 if the interrupt is masked (cannot be delivered
88 * Pending flag, 1 bit
[all …]
|
| /Documentation/arch/x86/ |
| D | entry_64.rst | 16 for 64-bit, arch/x86/entry/entry_32.S for 32-bit and finally
17 arch/x86/entry/entry_64_compat.S which implements the 32-bit compatibility
18 syscall entry points and thus provides for 32-bit processes the
19 ability to execute syscalls when running on 64-bit kernels.
25 - system_call: syscall instruction from 64-bit code.
27 - entry_INT80_compat: int 0x80 from 32-bit or 64-bit code; compat syscall
30 - entry_INT80_compat, ia32_sysenter: syscall and sysenter from 32-bit
44 There are a few complexities here. The different x86-64 entries
|
| D | usb-legacy-support.rst | 27 3) If AMD64 64-bit mode is enabled, again system crashes often happen,
28 because the SMM BIOS isn't expecting the CPU to be in 64-bit mode. The
29 BIOS manufacturers only test with Windows, and Windows doesn't do 64-bit
|
| /Documentation/process/ |
| D | adding-syscalls.rst | 151 offset within a file, make its type ``loff_t`` so that 64-bit offsets can be
152 supported even on 32-bit architectures.
155 it needs to be governed by the appropriate Linux capability bit (checked with
157 page. Choose an existing capability bit that governs related functionality,
159 under the same bit, as this goes against capabilities' purpose of splitting
170 system call parameters that are explicitly 64-bit fall on odd-numbered
171 arguments (i.e. parameter 1, 3, 5), to allow use of contiguous pairs of 32-bit
272 For most system calls the same 64-bit implementation can be invoked even when
273 the userspace program is itself 32-bit; even if the system call's parameters
277 needed to cope with size differences between 32-bit and 64-bit.
[all …]
|
| /Documentation/devicetree/bindings/timer/ |
| D | ti,keystone-timer.txt | 3 This document provides bindings for the 64-bit timer in the KeyStone
4 architecture devices. The timer can be configured as a general-purpose 64-bit
5 timer, dual general-purpose 32-bit timers. When configured as dual 32-bit
|
| D | ti,da830-timer.yaml | 13 This is a 64-bit timer found on TI's DaVinci architecture devices. The timer
14 can be configured as a general-purpose 64-bit timer, dual general-purpose
15 32-bit timers. When configured as dual 32-bit timers, each half can operate
|
| /Documentation/translations/it_IT/process/ |
| D | adding-syscalls.rst | 168 tipo cosicché scostamenti a 64-bit potranno essere supportati anche su
169 architetture a 32-bit.
172 funzioni riservate, allora dev'essere gestita da un opportuno bit di privilegio
174 :manpage:`capabilities(7)`. Scegliete un bit di privilegio già esistente per
176 funzionalità vagamente collegate dietro lo stesso bit, in quanto va contro il
188 di sistema con argomenti a 64-bit viene semplificata se questi argomenti
190 l'uso di coppie contigue di registri a 32-bit. (Questo non conta se gli
303 Per molte chiamate di sistema, la stessa implementazione a 64-bit può essere
304 invocata anche quando il programma in spazio utente è a 32-bit; anche se la
310 dimensioni fra 32-bit e 64-bit.
[all …]
|
| /Documentation/translations/sp_SP/process/ |
| D | adding-syscalls.rst | 172 tipo ``loff_t`` para que movimientos de 64-bit puedan ser soportados
173 incluso en arquitecturas de 32-bit.
177 bit linux apropiada (revisado con una llamada a ``capable()``), como se
192 un manejo más sencillo si los parámetros que son explícitamente 64-bit
304 Para la mayoría de llamadas al sistema la misma implementación 64-bit puede
305 ser invocada incluso cuando el programa de userspace es en si mismo 32-bit;
310 compatibilidad para lidiar con las diferencias de tamaño entre 32-bit y
311 64-bit.
313 La primera es si el kernel 64-bit también soporta programas del userspace
314 32-bit, y por lo tanto necesita analizar areas de memoria del (``__user``)
[all …]
|
| /Documentation/devicetree/bindings/powerpc/opal/ |
| D | power-mgt.txt | 41 Array of unsigned 32-bit values containing the values of the
61 Array of unsigned 32-bit values containing the values of the
66 Array of unsigned 32-bit values containing the values of the
74 Array of unsigned 64-bit values containing the values for the
79 Array of unsigned 64-bit values containing the masks
107 Array of unsigned 64-bit values containing the pmicr values
108 for the idle states in ibm,cpu-idle-state-names. This 64-bit
115 Array of unsigned 64-bit values containing the mask indicating
|
| /Documentation/scsi/ |
| D | aic7xxx.rst | 26 aic7770 10 EISA/VL 10MHz 16Bit 4 1
27 aic7850 10 PCI/32 10MHz 8Bit 3
28 aic7855 10 PCI/32 10MHz 8Bit 3
29 aic7856 10 PCI/32 10MHz 8Bit 3
30 aic7859 10 PCI/32 20MHz 8Bit 3
31 aic7860 10 PCI/32 20MHz 8Bit 3
32 aic7870 10 PCI/32 10MHz 16Bit 16
33 aic7880 10 PCI/32 20MHz 16Bit 16
34 aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8
35 aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 8
[all …]
|
| /Documentation/locking/ |
| D | robust-futex-ABI.rst | 43 consisting of three words. Each word is 32 bits on 32 bit arch's, or 64
44 bits on 64 bit arch's, and local byte order. Each thread should have
47 If a thread is running in 32 bit compatibility mode on a 64 native arch
48 kernel, then it can actually have two such structures - one using 32 bit
49 words for 32 bit compatibility mode, and one using 64 bit words for 64
50 bit native mode. The kernel, if it is a 64 bit kernel supporting 32 bit
63 is always a 32 bit word, unlike the other words above. The 'lock
79 The 'lock word' is always 32 bits, and is intended to be the same 32 bit
89 the kernel will walk this list, mark any such locks with a bit
162 1) if bit 31 (0x80000000) is set in that word, then attempt a futex
[all …]
|
| /Documentation/arch/mips/ |
| D | booting.rst | 21 aligned on a 64 bit boundary.
27 This convention is defined for 32-bit systems only, as there are not
28 currently any 64-bit BMIPS implementations.
|
12345678910>>...19