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/Documentation/i2c/
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/Documentation/devicetree/bindings/display/
Dsimple-framebuffer.yaml97 * `a1r5g5b5` - 16-bit pixels, d[15]=a, d[14:10]=r, d[9:5]=g, d[4:0]=b
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/Documentation/translations/zh_CN/arch/loongarch/
Dintroduction.rst153 0x310+8n (0≤n≤7) 内存读写监视点n配置1 MWPnCFG1
154 0x311+8n (0≤n≤7) 内存读写监视点n配置2 MWPnCFG2
155 0x312+8n (0≤n≤7) 内存读写监视点n配置3 MWPnCFG3
156 0x313+8n (0≤n≤7) 内存读写监视点n配置4 MWPnCFG4
159 0x390+8n (0≤n≤7) 取指监视点n配置1 FWPnCFG1
160 0x391+8n (0≤n≤7) 取指监视点n配置2 FWPnCFG2
161 0x392+8n (0≤n≤7) 取指监视点n配置3 FWPnCFG3
162 0x393+8n (0≤n≤7) 取指监视点n配置4 FWPnCFG4
205 ADD.W SUB.W ADDI.W ADD.D SUB.D ADDI.D
209 MUL.D MULH.D MULH.DU DIV.D DIV.DU MOD.D MOD.DU
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/Documentation/translations/zh_TW/arch/loongarch/
Dintroduction.rst153 0x310+8n (0≤n≤7) 內存讀寫監視點n配置1 MWPnCFG1
154 0x311+8n (0≤n≤7) 內存讀寫監視點n配置2 MWPnCFG2
155 0x312+8n (0≤n≤7) 內存讀寫監視點n配置3 MWPnCFG3
156 0x313+8n (0≤n≤7) 內存讀寫監視點n配置4 MWPnCFG4
159 0x390+8n (0≤n≤7) 取指監視點n配置1 FWPnCFG1
160 0x391+8n (0≤n≤7) 取指監視點n配置2 FWPnCFG2
161 0x392+8n (0≤n≤7) 取指監視點n配置3 FWPnCFG3
162 0x393+8n (0≤n≤7) 取指監視點n配置4 FWPnCFG4
205 ADD.W SUB.W ADDI.W ADD.D SUB.D ADDI.D
209 MUL.D MULH.D MULH.DU DIV.D DIV.DU MOD.D MOD.DU
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/Documentation/RCU/Design/Memory-Ordering/
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/Documentation/gpu/amdgpu/display/
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/Documentation/RCU/Design/Expedited-Grace-Periods/
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74 id="path3852-7"
75 d="M 0,0 5,-5 -12.5,0 5,5 0,0 z"
84 id="Arrow2Lend-7"
90d="M 8.7185878,4.0337352 -2.2072895,0.01601326 8.7185884,-4.0017078 c -1.7454984,2.3720609 -1.7354…
104d="M 8.7185878,4.0337352 -2.2072895,0.01601326 8.7185884,-4.0017078 c -1.7454984,2.3720609 -1.7354…
118d="M 8.7185878,4.0337352 -2.2072895,0.01601326 8.7185884,-4.0017078 c -1.7454984,2.3720609 -1.7354…
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146d="M 8.7185878,4.0337352 -2.2072895,0.01601326 8.7185884,-4.0017078 c -1.7454984,2.3720609 -1.7354…
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/Documentation/arch/loongarch/
Dintroduction.rst172 0x310+8n (0≤n≤7) Memory Load/Store WatchPoint n MWPnCFG1
174 0x311+8n (0≤n≤7) Memory Load/Store WatchPoint n MWPnCFG2
176 0x312+8n (0≤n≤7) Memory Load/Store WatchPoint n MWPnCFG3
178 0x313+8n (0≤n≤7) Memory Load/Store WatchPoint n MWPnCFG4
184 0x390+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG1
186 0x391+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG2
188 0x392+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG3
190 0x393+8n (0≤n≤7) Instruction Fetch WatchPoint n FWPnCFG4
238 ADD.W SUB.W ADDI.W ADD.D SUB.D ADDI.D
242 MUL.D MULH.D MULH.DU DIV.D DIV.DU MOD.D MOD.DU
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/Documentation/networking/device_drivers/can/ctu/
Dfsm_txt_buffer_user.svg5 …<path transform="scale(-.6)" d="m8.71859 4.03374-10.9259-4.01772 10.9259-4.01772c-1.7455 2.37206-1…
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11 …<path transform="scale(-.6)" d="m8.71859 4.03374-10.9259-4.01772 10.9259-4.01772c-1.7455 2.37206-1…
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26 …e(.6) rotate(180) translate(0)" d="m8.71859 4.03374-10.9259-4.01772 10.9259-4.01772c-1.7455 2.3720…
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32 …e(.6) rotate(180) translate(0)" d="m8.71859 4.03374-10.9259-4.01772 10.9259-4.01772c-1.7455 2.3720…
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/Documentation/misc-devices/
Doxsemi-tornado.rst30 setting bit 4 of the EFR. In that mode setting bit 7 in the MCR enables
44 from the requested rate (d), and the values of the oversampling rate
50 r: 15625000, a: 15625000.00, d: 0.0000%, tcr: 4, cpr: 1.000, div: 1
51 r: 12500000, a: 12500000.00, d: 0.0000%, tcr: 5, cpr: 1.000, div: 1
52 r: 10416666, a: 10416666.67, d: 0.0000%, tcr: 6, cpr: 1.000, div: 1
53 r: 8928571, a: 8928571.43, d: 0.0000%, tcr: 7, cpr: 1.000, div: 1
54 r: 7812500, a: 7812500.00, d: 0.0000%, tcr: 8, cpr: 1.000, div: 1
55 r: 4000000, a: 4000000.00, d: 0.0000%, tcr: 5, cpr: 3.125, div: 1
56 r: 3686400, a: 3676470.59, d: -0.2694%, tcr: 8, cpr: 2.125, div: 1
57 r: 3500000, a: 3496503.50, d: -0.0999%, tcr: 13, cpr: 1.375, div: 1
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/Documentation/devicetree/bindings/clock/
Dsilabs,si5341.txt6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
34 "silabs,si5340" - Si5340 A/B/C/D
35 "silabs,si5341" - Si5341 A/B/C/D
36 "silabs,si5342" - Si5342 A/B/C/D
37 "silabs,si5344" - Si5344 A/B/C/D
38 "silabs,si5345" - Si5345 A/B/C/D
156 clocks = <&si5341 0 7>; /* Output 7 */
158 /* Set output 7 to use syntesizer 3 as its parent */
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