Searched +full:8 +full:- +full:pin (Results 1 – 25 of 342) sorted by relevance
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,mxs-pinctrl.txt | 1 * Freescale MXS Pin Controller
3 The pins controlled by mxs pin controller are organized in banks, each bank
4 has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th
6 voltage and pull-up.
9 - compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
10 - reg: Should contain the register physical address and length for the
11 pin controller.
13 Please refer to pinctrl-bindings.txt in this directory for details of the
16 The node of mxs pin controller acts as a container for an arbitrary number of
20 information about pull-up. For this reason, even seemingly boolean values are
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| D | sunplus,sp7021-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/sunplus,sp7021-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Sunplus SP7021 Pin Controller
11 - Dvorkin Dmitry <dvorkin@tibbo.com>
12 - Wells Lu <wellslutw@gmail.com>
15 The Sunplus SP7021 pin controller is used to control SoC pins. Please
16 refer to pinctrl-bindings.txt in this directory for details of the common
23 (1) function-group pins:
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| D | renesas,rza2-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rza2-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/A2 combined Pin and GPIO controller
10 - Chris Brandt <chris.brandt@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
14 The Renesas SoCs of the RZ/A2 series feature a combined Pin and GPIO
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
17 Each port features up to 8 pins, each of them configurable for GPIO function
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| D | renesas,rzn1-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/N1 Pin Controller
10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
16 - enum:
17 - renesas,r9a06g032-pinctrl # RZ/N1D
18 - renesas,r9a06g033-pinctrl # RZ/N1S
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| D | renesas,rzv2m-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzv2m-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/V2M combined Pin and GPIO controller
10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
11 - Geert Uytterhoeven <geert+renesas@glider.be>
14 The Renesas RZ/V2M SoC features a combined Pin and GPIO controller.
15 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
18 Up to 8 different alternate function modes exist for each single pin.
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| D | cortina,gemini-pinctrl.txt | 1 Cortina Systems Gemini pin controller
3 This pin controller is found in the Cortina Systems Gemini SoC family,
4 see further arm/gemini.txt. It is a purely group-based multiplexing pin
7 The pin controller node must be a subnode of the system controller node.
10 - compatible: "cortina,gemini-pinctrl"
12 Subnodes of the pin controller contain pin control multiplexing set-up
13 and pin configuration of individual pins.
15 Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes
16 and generic pin config nodes.
19 - skew-delay is supported on the Ethernet pins
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| D | brcm,bcm2835-gpio.txt | 7 - compatible: "brcm,bcm2835-gpio"
8 - compatible: should be one of:
9 "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl
10 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
11 "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl
12 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
13 - reg: Should contain the physical address of the GPIO module's registers.
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and the
17 - bit 0 specifies polarity (0 for normal, 1 for inverted)
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| D | renesas,rzg2l-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/{G2L,V2L} combined Pin and GPIO controller
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
14 The Renesas SoCs of the RZ/{G2L,V2L} alike series feature a combined Pin and
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
17 Each port features up to 8 pins, each of them configurable for GPIO function
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| D | pinctrl-mcp23s08.txt | 2 8-/16-bit I/O expander with serial interface (I2C/SPI)
5 - compatible : Should be
6 - "mcp,mcp23s08" (DEPRECATED) for 8 GPIO SPI version
7 - "mcp,mcp23s17" (DEPRECATED) for 16 GPIO SPI version
8 - "mcp,mcp23008" (DEPRECATED) for 8 GPIO I2C version or
9 - "mcp,mcp23017" (DEPRECATED) for 16 GPIO I2C version of the chip
11 - "microchip,mcp23s08" for 8 GPIO SPI version
12 - "microchip,mcp23s17" for 16 GPIO SPI version
13 - "microchip,mcp23s18" for 16 GPIO SPI version
14 - "microchip,mcp23008" for 8 GPIO I2C version or
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| D | brcm,nsp-gpio.txt | 4 - compatible:
5 Must be "brcm,nsp-gpio-a"
7 - reg:
11 - #gpio-cells:
12 Must be two. The first cell is the GPIO pin number (within the
13 controller's pin space) and the second cell is used for the following:
16 - gpio-controller:
19 - ngpios:
23 - interrupts:
26 - interrupt-controller:
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| /Documentation/devicetree/bindings/net/ |
| D | mdio-mux-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
17 - $ref: /schemas/net/mdio-mux.yaml#
21 const: mdio-mux-gpio
30 - compatible
31 - gpios
36 - |
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/ |
| D | pincfg.txt | 1 * Pin configuration nodes
4 - pio-map : array of pin configurations. Each pin is defined by 6
5 integers. The six numbers are respectively: port, pin, dir,
7 - port : port number of the pin; 0-6 represent port A-G in UM.
8 - pin : pin number in the port.
9 - dir : direction of the pin, should encode as follows:
11 0 = The pin is disabled
12 1 = The pin is an output
13 2 = The pin is an input
14 3 = The pin is I/O
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| /Documentation/devicetree/bindings/sound/ |
| D | adi,adau1701.txt | 5 - compatible: Should contain "adi,adau1701"
6 - reg: The i2c address. Value depends on the state of ADDR0
11 - reset-gpio: A GPIO spec to define which pin is connected to the
12 chip's !RESET pin. If specified, the driver will
14 - adi,pll-mode-gpios: An array of two GPIO specs to describe the GPIOs
19 - adi,pin-config: An array of 12 numerical values selecting one of the
20 pin configurations as described in the datasheet,
22 to be prefixed with '/bits/ 8'.
23 - avdd-supply: Power supply for AVDD, providing 3.3V
24 - dvdd-supply: Power supply for DVDD, providing 3.3V
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| /Documentation/driver-api/ |
| D | pin-control.rst | 2 PINCTRL (PIN CONTROL) subsystem
5 This document outlines the pin control subsystem in Linux
9 - Enumerating and naming controllable pins
11 - Multiplexing of pins, pads, fingers (etc) see below for details
13 - Configuration of pins, pads, fingers (etc), such as software-controlled
14 biasing and driving mode specific pins, such as pull-up, pull-down, open drain,
17 Top-level interface
22 - A PIN CONTROLLER is a piece of hardware, usually a set of registers, that
26 - PINS are equal to pads, fingers, balls or whatever packaging input or
28 in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
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| /Documentation/devicetree/bindings/gpio/ |
| D | nxp,lpc1850-gpio.txt | 2 -----------------------------------------------------
5 - compatible : Should be "nxp,lpc1850-gpio"
6 - reg : List of addresses and lengths of the GPIO controller
8 - reg-names : Should be "gpio", "gpio-pin-ic", "gpio-group0-ic" and
9 "gpio-gpoup1-ic"
10 - clocks : Phandle and clock specifier pair for GPIO controller
11 - resets : Phandle and reset specifier pair for GPIO controller
12 - gpio-controller : Marks the device node as a GPIO controller
13 - #gpio-cells : Should be two:
14 - The first cell is the GPIO line number
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| D | cavium-octeon-gpio.txt | 4 - compatible: "cavium,octeon-3860-gpio"
8 - reg: The base address of the GPIO unit's register bank.
10 - gpio-controller: This is a GPIO controller.
12 - #gpio-cells: Must be <2>. The first cell is the GPIO pin.
14 - interrupt-controller: The GPIO controller is also an interrupt
18 - #interrupt-cells: Must be <2>. The first cell is the GPIO pin
21 1 - edge triggered on the rising edge.
22 2 - edge triggered on the falling edge
23 4 - level triggered active high.
24 8 - level triggered active low.
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| D | gpio-max3191x.txt | 4 - compatible: Must be one of:
11 - reg: Chip select number.
12 - gpio-controller: Marks the device node as a GPIO controller.
13 - #gpio-cells: Should be two. For consumer use see gpio.txt.
16 - #daisy-chained-devices:
17 Number of chips in the daisy-chain (default is 1).
18 - maxim,modesel-gpios: GPIO pins to configure modesel of each chip.
19 The number of GPIOs must equal "#daisy-chained-devices"
20 (if each chip is driven by a separate pin) or 1
21 (if all chips are wired to the same pin).
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | tda1997x.txt | 1 Device-Tree bindings for the NXP TDA1997x HDMI receiver
6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
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| /Documentation/devicetree/bindings/regulator/ |
| D | lp872x.txt | 4 - compatible: "ti,lp8720" or "ti,lp8725"
5 - reg: I2C slave address. 0x7d = LP8720, 0x7a = LP8725
8 - ti,general-config: the value of LP872X_GENERAL_CFG register (u8)
10 bit[2]: BUCK output voltage control by external DVS pin or register
11 1 = external pin, 0 = bit7 of register 08h
12 bit[1]: sleep control by external DVS pin or register
13 1 = external pin, 0 = bit6 of register 08h
20 bit[2]: BUCK1 output voltage control by external DVS pin or register
27 - ti,update-config: define it when LP872X_GENERAL_CFG register should be set
28 - ti,dvs-gpio: GPIO specifier for external DVS pin control of LP872x devices.
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | adi,ad7606.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
14 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7605-4.pdf
15 https://www.analog.com/media/en/technical-documentation/data-sheets/ad7606_7606-6_7606-4.pdf
16 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7606B.pdf
17 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7616.pdf
22 - adi,ad7605-4
23 - adi,ad7606-4
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| D | renesas,rcar-gyroadc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/renesas,rcar-gyroadc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car GyroADC
10 - Marek Vasut <marek.vasut+renesas@gmail.com>
13 The GyroADC block is a reduced SPI block with up to 8 chipselect lines,
15 are sampled by the GyroADC block in a round-robin fashion and the result
23 - enum:
24 - renesas,r8a7791-gyroadc
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| D | adi,ad7091r5.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD7091R-2/-4/-5/-8 Multi-Channel 12-Bit ADCs
10 - Michael Hennerich <michael.hennerich@analog.com>
11 - Marcelo Schmitt <marcelo.schmitt@analog.com>
14 Analog Devices AD7091R5 4-Channel 12-Bit ADC supporting I2C interface
15 https://www.analog.com/media/en/technical-documentation/data-sheets/ad7091r-5.pdf
16 Analog Devices AD7091R-2/AD7091R-4/AD7091R-8 2-/4-/8-Channel 12-Bit ADCs
18 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7091R-2_7091R-4_7091R-8.pdf
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| /Documentation/driver-api/media/drivers/ |
| D | saa7134-devel.rst | 1 .. SPDX-License-Identifier: GPL-2.0
10 ----------------
14 - 32.11 MHz -> .audio_clock=0x187de7
15 - 24.576MHz -> .audio_clock=0x200000 (xtal * .audio_clock = 51539600)
19 - saa7130 - low-price chip, doesn't have mute, that is why all those
22 - saa7134 - usual chip
24 - saa7133/35 - saa7135 is probably a marketing decision, since all those
28 --------------
32 - LifeView FlyTV Platinum FM (LR214WF)
34 - GP27 MDT2005 PB4 pin 10
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| /Documentation/input/devices/ |
| D | joystick-parport.rst | 3 .. _joystick-parport:
9 :Copyright: |copy| 1998-2000 Vojtech Pavlik <vojtech@ucw.cz>
10 :Copyright: |copy| 1998 Andree Borrmann <a.borrmann@tu-bs.de>
18 Any information in this file is provided as-is, without any guarantee that
36 Many console and 8-bit computer gamepads and joysticks are supported. The
40 ------------
59 for your pads, use either keyboard or joystick port, and make a pass-through
64 some data pin. For most gamepad and parport implementations only one pin is
65 needed, and I'd recommend pin 9 for that, the highest data bit. On the other
67 port, anything between and including pin 4 and pin 9 will work::
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| /Documentation/devicetree/bindings/usb/ |
| D | maxim,max3421.txt | 1 Maxim Integrated SPI-based USB 2.0 host controller MAX3421E
4 - compatible: Should be "maxim,max3421"
5 - spi-max-frequency: maximum frequency for this device must not exceed 26 MHz.
6 - reg: chip select number to which this device is connected.
7 - maxim,vbus-en-pin: <GPOUTx ACTIVE_LEVEL>
8 GPOUTx is the number (1-8) of the GPOUT pin of MAX3421E to drive Vbus.
10 - interrupts: the interrupt line description for the interrupt controller.
19 maxim,vbus-en-pin = <3 1>;
20 spi-max-frequency = <26000000>;
21 interrupt-parent = <&PIC>;
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