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/Documentation/gpu/
Dafbc.rst42 * Component 0: R(8)
43 * Component 1: G(8)
44 * Component 2: B(8)
45 * Component 3: A(8)
49 * Component 0: R(8)
50 * Component 1: G(8)
51 * Component 2: B(8)
55 * Component 0: Y(8)
56 * Component 1: Cb(8, 2x1 subsampled)
57 * Component 2: Cr(8, 2x1 subsampled)
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/Documentation/userspace-api/media/rc/
Drc-protos.rst17 Other things can be encoded too. Some IR protocols encode a toggle bit; this
20 toggle bit will invert from one IR message to the next.
41 * - rc-5 bit
43 - scancode bit
51 - Start bit, always set
57 - 2nd start bit in rc5, re-used as 6th command bit
63 - Toggle bit
67 - 8 to 13
78 where there the second stop bit is the 6th command bit, but inverted.
80 schemes. This bit is stored in bit 6 of the scancode, inverted. This is
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/Documentation/devicetree/bindings/media/i2c/
Dtda1997x.txt6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
17 - YUV444 12bit per color (36 bits total): Y[11:0] Cb[11:0] Cr[11:0]
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/Documentation/userspace-api/media/v4l/
Dmetafmt-generic.rst17 .. _v4l2-meta-fmt-generic-8:
22 The V4L2_META_FMT_GENERIC_8 format is a plain 8-bit metadata format. This format
23 is used on CSI-2 for 8 bits per :term:`Data Unit`.
26 packed into one 16-bit Data Unit. Otherwise the 16 bits per pixel dataformat is
37 :widths: 12 8 8 8 8
55 V4L2_META_FMT_GENERIC_CSI2_10 contains 8-bit generic metadata packed in 10-bit
74 .. tabularcolumns:: |p{2.4cm}|p{1.2cm}|p{1.2cm}|p{1.2cm}|p{1.2cm}|p{.8cm}|
79 :widths: 12 8 8 8 8 8
99 V4L2_META_FMT_GENERIC_CSI2_12 contains 8-bit generic metadata packed in 12-bit
118 .. tabularcolumns:: |p{2.4cm}|p{1.2cm}|p{1.2cm}|p{1.2cm}|p{1.2cm}|p{.8cm}|p{.8cm}|
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/Documentation/devicetree/bindings/media/
Dti,da850-vpif.txt18 VPIF has a 16-bit parallel bus input, supporting 2 8-bit channels or a
19 single 16-bit channel. It should contain one or two port child nodes
25 Example using 2 8-bit input channels, one of which is connected to an
36 bus-width = <8>;
42 bus-width = <8>;
43 data-shift = <8>;
49 bus-width = <8>;
69 /* VPIF channel 0 (lower 8-bits) */
71 bus-width = <8>;
86 bus-width = <8>;
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Dti-am437x-vpfe.txt15 1 - 8 Bit BT656 Interface.
16 2 - 10 Bit BT656 Interface.
17 3 - YCbCr 8 Bit Interface.
18 4 - YCbCr 16 Bit Interface.
41 bus-width = <8>;
57 bus-width = <8>;
/Documentation/staging/
Dcrc32.rst17 subtract, we just xor. Thus, we tend to get a bit sloppy about
21 To produce a 32-bit CRC, the divisor is actually a 33-bit CRC polynomial.
22 Since it's 33 bits long, bit 32 is always going to be set, so usually the
23 CRC is written in hex with the most significant bit omitted. (If you're
30 little-endian; the most significant bit (sometimes used for parity)
34 Just like with ordinary division, you proceed one digit (bit) at a time.
35 Each step of the division you take one more digit (bit) of the dividend
39 and to make the XOR cancel, it's just a copy of bit 32 of the remainder.
42 throw the quotient bit away, but subtract the appropriate multiple of
44 ready to process the next bit.
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/Documentation/ABI/testing/
Dsysfs-class-net-peak_usb14 device type, the identifier has a length of 8 or 32 bit. The
15 value read from this attribute is always an 8 digit 32 bit
17 supports an 8 bit identifier, the upper 24 bit of the value are
Dsysfs-driver-jz4780-efuse5 The SoC has a one time programmable 8K efuse that is
10 0x000 64 bit Random Number
11 0x008 128 bit Ingenic Chip ID
12 0x018 128 bit Customer ID
13 0x028 3520 bit Reserved
14 0x1E0 8 bit Protect Segment
15 0x1E1 2296 bit HDMI Key
16 0x300 2048 bit Security boot key
/Documentation/devicetree/bindings/gpio/
Dgpio-74xx-mmio.txt5 "ti,741g125": for 741G125 (1-bit Input),
6 "ti,741g174": for 741G74 (1-bit Output),
7 "ti,742g125": for 742G125 (2-bit Input),
8 "ti,7474" : for 7474 (2-bit Output),
9 "ti,74125" : for 74125 (4-bit Input),
10 "ti,74175" : for 74175 (4-bit Output),
11 "ti,74365" : for 74365 (6-bit Input),
12 "ti,74174" : for 74174 (6-bit Output),
13 "ti,74244" : for 74244 (8-bit Input),
14 "ti,74273" : for 74273 (8-bit Output),
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/Documentation/devicetree/bindings/mfd/
Dmc13xxx.txt37 8 : Blue 2
55 sw1a : regulator SW1A (register 24, bit 0)
56 sw1b : regulator SW1B (register 25, bit 0)
57 sw2a : regulator SW2A (register 26, bit 0)
58 sw2b : regulator SW2B (register 27, bit 0)
59 sw3 : regulator SW3 (register 29, bit 20)
60 vaudio : regulator VAUDIO (register 32, bit 0)
61 viohi : regulator VIOHI (register 32, bit 3)
62 violo : regulator VIOLO (register 32, bit 6)
63 vdig : regulator VDIG (register 32, bit 9)
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/Documentation/devicetree/bindings/dma/stm32/
Dst,stm32-dma.yaml11 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
17 3. A 32bit mask specifying the DMA channel configuration which are device
19 -bit 9: Peripheral Increment Address
22 -bit 10: Memory Increment Address
25 -bit 15: Peripheral Increment Offset Size
27 0x1: offset size is fixed to 4 (32-bit alignment)
28 -bit 16-17: Priority level
33 4. A 32bit bitfield value specifying DMA features which are device dependent:
34 -bit 0-1: DMA FIFO threshold selection
39 -bit 2: DMA direct mode
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Dst,stm32-mdma.yaml21 3. A 32bit mask specifying the DMA channel configuration
22 -bit 0-1: Source increment mode
26 -bit 2-3: Destination increment mode
30 -bit 8-9: Source increment offset size
31 0x0: byte (8bit)
32 0x1: half-word (16bit)
33 0x2: word (32bit)
34 0x3: double-word (64bit)
35 -bit 10-11: Destination increment offset size
36 0x0: byte (8bit)
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/Documentation/devicetree/bindings/timer/
Drenesas,cmt.yaml14 The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock
28 - renesas,r8a7740-cmt0 # 32-bit CMT0 on R-Mobile A1
29 - renesas,r8a7740-cmt1 # 48-bit CMT1 on R-Mobile A1
30 - renesas,r8a7740-cmt2 # 32-bit CMT2 on R-Mobile A1
31 - renesas,r8a7740-cmt3 # 32-bit CMT3 on R-Mobile A1
32 - renesas,r8a7740-cmt4 # 32-bit CMT4 on R-Mobile A1
33 - renesas,sh73a0-cmt0 # 32-bit CMT0 on SH-Mobile AG5
34 - renesas,sh73a0-cmt1 # 48-bit CMT1 on SH-Mobile AG5
35 - renesas,sh73a0-cmt2 # 32-bit CMT2 on SH-Mobile AG5
36 - renesas,sh73a0-cmt3 # 32-bit CMT3 on SH-Mobile AG5
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/Documentation/devicetree/bindings/leds/
Dregister-bit-led.yaml4 $id: http://devicetree.org/schemas/leds/register-bit-led.yaml#
7 title: Register Bit LEDs
13 Register bit leds are used with syscon multifunctional devices where single
14 bits in a certain register can turn on/off a single LED. The register bit LEDs
25 The unit-address is in the form of @<reg addr>,<bit offset>
29 const: register-bit-led
38 bit mask for the bit controlling this LED in the register
69 led@8,0 {
70 compatible = "register-bit-led";
78 led@8,1 {
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/Documentation/devicetree/bindings/clock/
Darm,syscon-icst.yaml19 an ICST clock request after a write to the 32 bit register at an offset
25 connects the low 8 bits of the VDW (missing one bit), hard-wires RDW to
37 Integrator/AP 22 1 Bit 8 0, rest variable
40 Integrator/AP 46 3 Bit 8 0, rest variable
46 Integrator/CP 22 variable Bit 8 0, rest variable
49 Integrator/CP 22 variable Bit 8 0, rest variable
/Documentation/virt/kvm/devices/
Dxics.rst32 sources, each identified by a 20-bit source number, and a set of
41 KVM_GET_ONE_REG and KVM_SET_ONE_REG ioctls on the vcpu. The 64 bit
47 * Pending interrupt priority, 8 bits
50 * Pending IPI (inter-processor interrupt) priority, 8 bits
56 * Current processor priority, 8 bits
63 the interrupt source number. The 64 bit state word has the following
71 * Priority, 8 bits
77 * Level sensitive flag, 1 bit
79 This bit is 1 for a level-sensitive interrupt source, or 0 for
82 * Masked flag, 1 bit
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/Documentation/devicetree/bindings/clock/ti/
Dautoidle.txt5 and a configuration bit setting. Autoidle clock is never an individual
13 - ti,autoidle-shift : bit shift of the autoidle enable bit
14 - ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0
22 ti,autoidle-shift = <8>;
25 ti,invert-autoidle-bit;
33 ti,autoidle-shift = <8>;
36 ti,invert-autoidle-bit;
/Documentation/devicetree/bindings/edac/
Daspeed-sdram-edac.txt6 The memory controller supports SECDED (single bit error correction, double bit
7 error detection) and single bit error auto scrubbing by reserving 8 bits for
8 every 64 bit word (effectively reducing available memory to 8/9).
/Documentation/fb/
Darkfb.rst19 * 4 bpp pseudocolor modes (with 18bit palette, two variants)
20 * 8 bpp pseudocolor mode (with 18bit palette)
31 hardware). This limitation is not enforced by driver. Text mode supports 8bit
32 wide fonts only (hardware limitation) and 16bit tall fonts (driver
39 8bit wide fonts only (driver limitation).
54 * support for fontwidths != 8 in 4 bpp modes
/Documentation/bpf/
Dclassic_vs_extended.rst16 pointer. Since 64-bit CPUs are passing arguments to functions via registers
20 sparcv9/mips64 have 7 - 8 registers for arguments; x86_64 has 6 callee saved
25 64-bit architectures.
27 On 32-bit architectures JIT may map programs that use only 32-bit arithmetic
35 - Register width increases from 32-bit to 64-bit:
37 Still, the semantics of the original 32-bit ALU operations are preserved
38 via 32-bit subregisters. All eBPF registers are 64-bit with 32-bit lower
39 subregisters that zero-extend into 64-bit if they are being written to.
43 32-bit architectures run 64-bit eBPF programs via interpreter.
44 Their JITs may convert BPF programs that only use 32-bit subregisters into
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/Documentation/arch/sparc/oradax/
Ddax-hv-api.txt83 bit fields and controls.
136 All CCBs begin with a common 32-bit header.
163 [10:8] Output/Destination address type
220 Both the Pipeline and Serial bits must be set in the source CCB. The Conditional bit must be set in…
224 bits set, and terminate at a CCB that has the Conditional bit set, but not the Pipeline bit.
252 …The primary input format code is a 4-bit field when it is used. There are 10 primary input formats…
257 …0x1 Fixed width bit packed Up to 15 bits (CCB version 0) or 23 bits (CCB vers…
258 … 1); bits are read most significant bit to least significant bit
264 … 0x5 Fixed width bit packed with run Up to 15 bits (CCB version 0) or 23 bits (CCB version
265 … length encoding 1); bits are read most significant bit to least significant bit
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/Documentation/devicetree/bindings/net/
Dlantiq,pef2256.yaml72 Data rate (bit per seconds) on the system highway.
86 The pef2256 delivers a full frame (32 8-bit time-slots in E1 and 24 8-bit
87 time-slots 8 8-bit signaling in E1/J1) every 125us. This lead to a data
88 rate of 2048000 bit/s. When lantiq,data-rate-bps is more than 2048000
89 bit/s, the data (all 32 8-bit) present in the frame are interleave with
118 sub-nodes that involve the codec. The codec uses 8-bit time-slots.
119 'dai-tdm-tdm-slot-with' must be set to 8.
150 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
193 dai-tdm-slot-width = <8>;
207 dai-tdm-slot-width = <8>;
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/Documentation/core-api/
Dpacking.rst15 definitions from the hardware documentation into bit field indices for the
18 (sometimes even 64 bit ones). This creates the inconvenience of having to
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
44 perspective, bit 63 always means bit offset 7 of byte 7, albeit only
45 logically. The question is: where do we lay this bit out in memory?
57 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
63 bit i corresponds to the number 2^i. This is also referred to in the code
73 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7
77 inverts bit offsets inside a byte.
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/Documentation/networking/device_drivers/cellular/qualcomm/
Drmnet.rst36 Bit 0 1 2-7 8-15 16-31
39 Bit 32-x
42 Command (1)/ Data (0) bit value is to indicate if the packet is a MAP command
62 Bit 0 1 2-7 8-15 16-31
65 Bit 32-(x-33) (x-32)-x
68 Command (1)/ Data (0) bit value is to indicate if the packet is a MAP command
87 Bit 0-14 15 16-31
90 Bit 31-47 48-64
95 Valid bit indicates whether the partial checksum is calculated and is valid.
115 Bit 0 1 2-7 8-15 16-31
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