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/Documentation/userspace-api/media/v4l/
Dsubdev-formats.rst165 on parallel busses for transferring an 8 bits per sample BGR data, whereas on
201 8-bit samples per pixel with the most significant bits (padding, red and
257 - 8
1835 - r\ :sub:`8`
1845 - g\ :sub:`8`
1855 - b\ :sub:`8`
1921 - 8
2020 - r\ :sub:`8`
2032 - g\ :sub:`8`
2044 - b\ :sub:`8`
[all …]
Dmetafmt-vsp1-hgo.rst53 - [15:8]
65 * - 8
67 - B/Cb/V max [7:0]
69 - B/Cb/V min [7:0]
75 - :cspan:`4` B/Cb/V sum [31:0]
89 - :cspan:`4` B/Cb/V bin 0 [31:0]
93 - :cspan:`4` B/Cb/V bin 63 [31:0]
104 - [15:8]
113 * - 8
129 - [15:8]
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/Documentation/devicetree/bindings/mfd/
Dmaxim,max8998.yaml171 regulator-name = "VALIVE_1.2V";
178 regulator-name = "VUSB+MIPI_1.1V";
185 regulator-name = "VADC_3.3V";
191 regulator-name = "VTF_2.8V";
203 regulator-name = "VLCD+VMIPI_1.8V";
209 regulator-name = "VUSB+VDAC_3.3V";
216 regulator-name = "VCC_2.8V";
223 regulator-name = "VPLL_1.1V";
231 regulator-name = "CAM_AF_3.3V";
237 regulator-name = "PS_2.8V";
[all …]
Drichtek,rt4831.yaml16 For Display Bias Voltage DSVP and DSVN, the output range is about 4V to 6.5V.
36 Some usage directly tied this pin to follow VIO 1.8V power on sequence.
86 richtek,bled-ovp-sel = /bits/ 8 <RT4831_BLOVPLVL_21V>;
87 richtek,channel-use = /bits/ 8 <RT4831_BLED_ALLCHEN>;
/Documentation/hwmon/
Dadm1026.rst34 * gpio_fan: int array (min = 1, max = 8)
45 16 general purpose digital I/O lines, eight (8) fan speed sensors (8-bit),
47 all of the above. There is even 8k bytes of EEPROM memory on chip.
61 by 1, 2, 4 or 8. Not all RPM values can accurately be represented, so some
62 rounding is done. With a divider of 8, the slowest measurable speed of a
69 higher voltages directly. 3.3V, 5V, 12V, -12V and battery voltage all have
70 dedicated inputs. There are several inputs scaled to 0-3V full-scale range
72 a 0-2.5V full-scale range. A 2.5V or 1.82V reference voltage is provided
Dmax197.rst25 The A/D converters MAX197, and MAX199 are both 8-Channel, Multi-Range, 5V,
26 12-Bit DAS with 8+4 Bus Interface and Fault Protection.
28 The available ranges for the MAX197 are {0,-5V} to 5V, and {0,-10V} to 10V,
29 while they are {0,-2V} to 2V, and {0,-4V} to 4V on the MAX199.
Dsmsc47m192.rst35 These chips support 3 temperature channels and 8 voltage inputs
42 Voltages and temperatures are measured by an 8-bit ADC, the resolution
46 each voltage channel is 0V ... 255/192*(nominal voltage), the resolution
51 The +12V analog voltage input channel (in4_input) is multiplexed with
53 a +12V voltage measurement or a 5 bit CPU VID, but not both.
54 The default setting is to use the pin as 12V input, and use only 4 bit VID.
67 in0_input +2.5V voltage input
68 in1_input CPU voltage input (nominal 2.25V)
69 in2_input +3.3V voltage input
70 in3_input +5V voltage input
[all …]
Df71805f.rst67 Voltages are sampled by an 8-bit ADC with a LSB of 8 mV. The supported
68 range is thus from 0 to 2.040 V. Voltage values outside of this range
70 the chip's own power source (+3.3V), and is divided internally by a
83 in0 VCC VCC3.3V int. int. 2.00 1.65 V
84 in1 VIN1 VTT1.2V 10K - 1.00 1.20 V
85 in2 VIN2 VRAM 100K 100K 2.00 ~1.25 V [1]_
86 in3 VIN3 VCHIPSET 47K 100K 1.47 2.24 V [2]_
87 in4 VIN4 VCC5V 200K 47K 5.25 0.95 V
88 in5 VIN5 +12V 200K 20K 11.00 1.05 V
89 in6 VIN6 VCC1.5V 10K - 1.00 1.50 V
[all …]
/Documentation/fb/
Dviafb.modes29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
41 # 8 chars 3 lines
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
83 # 8 chars 3 lines
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
104 # 8 chars 3 lines
116 # D: 52.406 MHz, H: 61.800 kHz, V: 120.00 Hz
137 # D: 26.880 MHz, H: 30.000 kHz, V: 60.24 Hz
[all …]
/Documentation/devicetree/bindings/iio/adc/
Dadi,ad7091r5.yaml7 title: Analog Devices AD7091R-2/-4/-5/-8 Multi-Channel 12-Bit ADCs
16 Analog Devices AD7091R-2/AD7091R-4/AD7091R-8 2-/4-/8-Channel 12-Bit ADCs
18 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7091R-2_7091R-4_7091R-8.pdf
33 Provide VDD power to the sensor (VDD range is from 2.7V to 5.25V).
38 The V_drive voltage range is from 1.8V to 5.25V and must not exceed VDD by
39 more than 0.3V.
Dqcom,spmi-vadc.yaml103 - enum: [ 1, 3, 4, 6, 20, 8, 10, 16 ]
112 specified VADC will use the VDD reference (1.8V) and GND for
114 calibrated with 0.625V and 1.25V reference channels, also
118 the VDD reference (1.875V) and GND for channel calibration. If
119 property is not found, channel will be calibrated with 0V and 1.25V
158 4, 6, 8, 10 ]
162 enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512 ]
181 4, 6, 8, 10 ]
185 enum: [ 1, 2, 4, 8, 16 ]
204 4, 6, 8, 10, 16, 32, 64, 128 ]
[all …]
/Documentation/devicetree/bindings/sound/
Dqcom,wcd93xx-common.yaml18 description: A reference to the 1.8V buck supply
21 description: A reference to the 1.8V rx supply
24 description: A reference to the 1.8V I/O supply
27 description: A reference to the 3.8V mic bias supply
77 Array of 8 Voltage threshold values corresponding to headset
79 minItems: 8
80 maxItems: 8
Dfsl,sgtl5000.yaml44 values of 2k, 4k or 8k. If set to 0 it will be off. If this node is not
47 enum: [ 0, 2, 4, 8 ]
51 values from 1.25V to 3V by 250mV steps. If this node is not mentioned
52 or the value is unknown, then the value is set to 1.25V.
61 VDDIO 1.8V 2.5V 3.3V
74 VDDIO 1.8V 2.5V 3.3V
Dst,sta32x.txt16 - Vdda-supply: regulator spec, providing 3.3V
17 - Vdd3-supply: regulator spec, providing 3.3V
18 - Vcc-supply: regulator spec, providing 5V - 26V
32 This property has to be specified as '/bits/ 8' value.
41 This properties have to be specified as '/bits/ 8' values.
90 st,output-conf = /bits/ 8 <0x3>; // set output to 2-channel
93 st,ch1-output-mapping = /bits/ 8 <0>; // set channel 1 output ch 1
94 st,ch2-output-mapping = /bits/ 8 <0>; // set channel 2 output ch 1
95 st,ch3-output-mapping = /bits/ 8 <0>; // set channel 3 output ch 1
Dst,sta350.txt16 - vdd-dig-supply: regulator spec, providing 3.3V
17 - vdd-pll-supply: regulator spec, providing 3.3V
18 - vcc-supply: regulator spec, providing 5V - 26V
28 This property has to be specified as '/bits/ 8' value.
37 This properties have to be specified as '/bits/ 8' values.
110 are 1, 2, 4, 8, 16, 32, 64 and 128.
111 This property has to be specified as '/bits/ 8' value.
120 st,output-conf = /bits/ 8 <0x3>; // set output to 2-channel
123 st,ch1-output-mapping = /bits/ 8 <0>; // set channel 1 output ch 1
124 st,ch2-output-mapping = /bits/ 8 <0>; // set channel 2 output ch 1
[all …]
Dadi,adau1701.txt22 to be prefixed with '/bits/ 8'.
23 - avdd-supply: Power supply for AVDD, providing 3.3V
24 - dvdd-supply: Power supply for DVDD, providing 3.3V
36 adi,pin-config = /bits/ 8 <0x4 0x7 0x5 0x5 0x4 0x4
/Documentation/arch/riscv/
Dhwprobe.rst3 RISC-V Hardware Probing Interface
6 The RISC-V hardware probing interface is based around a single syscall, which
49 as defined by the RISC-V privileged architecture specification.
52 defined by the RISC-V privileged architecture specification.
55 defined by the RISC-V privileged architecture specification.
76 minimumNumber/maximumNumber, not minNum/maxNum") of the RISC-V ISA manual.
79 by version 2.2 of the RISC-V ISA manual.
81 * :c:macro:`RISCV_HWPROBE_IMA_V`: The V extension is supported, as defined by
82 version 1.0 of the RISC-V Vector extension manual.
128 defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
[all …]
/Documentation/devicetree/bindings/leds/backlight/
Dlp855x-backlight.yaml40 description: Regulator which controls the 3V rail.
91 dev-ctrl = /bits/ 8 <0x00>;
96 /* 4V OV, 4 output LED0 string enabled */
98 rom-addr = /bits/ 8 <0x14>;
99 rom-val = /bits/ 8 <0xcf>;
104 rom-addr = /bits/ 8 <0x15>;
105 rom-val = /bits/ 8 <0xc7>;
110 rom-addr = /bits/ 8 <0x19>;
111 rom-val = /bits/ 8 <0x0f>;
125 dev-ctrl = /bits/ 8 <0x85>;
[all …]
/Documentation/devicetree/bindings/media/xilinx/
Dxlnx,v-tpg.txt8 "xlnx,v-tpg-5.0" (TPG version 5.0)
9 "xlnx,v-tpg-6.0" (TPG version 6.0)
39 compatible = "xlnx,v-tpg-6.0", "xlnx,v-tpg-5.0";
54 xlnx,video-width = <8>;
64 xlnx,video-width = <8>;
/Documentation/userspace-api/media/dvb/
Ddvbstb.svg1 <?xml version="1.0" encoding="UTF-8"?>
3 …8 0 0 -.8 -10 0)" d="m0 0 5-5-17.5 5 17.5 5z" fill-rule="evenodd" stroke="#000" stroke-width="1pt"…
4 …v-9600h18400v9600z" fill="#fff"/><path id="path201" d="m14556 9614.1h-9200v-9600h18400v9600z" fill…
6 …th id="path225" d="m8485.1 4214.1h-2271v-2400h4541v2400z" fill="#fff"/><path id="path227" d="m8485…
7 …ath id="path242" d="m14385 4214.1h-2271v-2400h4541v2400z" fill="#fff"/><path id="path244" d="m1438…
8 …ath id="path259" d="m20385 4214.1h-2271v-2400h4541v2400z" fill="#fff"/><path id="path261" d="m2038…
9 …th id="path276" d="m8385.1 8214.1h-2271v-2400h4541v2400z" fill="#fff"/><path id="path278" d="m8385…
10 …ath id="path293" d="m14485 8214.1h-2271v-2400h4541v2400z" fill="#fff"/><path id="path295" d="m1448…
11 …ath id="path310" d="m20385 8214.1h-2271v-2400h4541v2400z" fill="#fff"/><path id="path312" d="m2038…
12 …<path id="path327" d="m17485 12614h-2271v-2400h4541v2400z" fill="#fff"/><path id="path329" d="m174…
/Documentation/iio/
Dad7380.rst47 ad7380-4 supports only an external reference voltage (2.5V to 3.3V). It must be
55 - Internal reference (2.5V)
56 - External reference (2.5V to 3.3V)
67 available: 1 (oversampling disabled)/2/4/8/16/32.
90 Single-ended chips of this family (ad7386/7/8(-4)) have a 2:1 multiplexer in
95 From an IIO point of view, all inputs are exported, i.e ad7386/7/8
96 export 4 channels and ad7386-4/7-4/8-4 export 8 channels.
100 Example for AD7386/7/8 (2 channels parts):
104 IIO | AD7386/7/8
/Documentation/devicetree/bindings/media/i2c/
Dovti,ov5640.yaml68 enum: [8, 10]
101 DOVDD-supply = <&vgen4_reg>; /* 1.8v */
102 AVDD-supply = <&vgen3_reg>; /* 2.8v */
103 DVDD-supply = <&vgen2_reg>; /* 1.5v */
131 DOVDD-supply = <&vgen4_reg>; /* 1.8v */
132 AVDD-supply = <&vgen3_reg>; /* 2.8v */
133 DVDD-supply = <&vgen2_reg>; /* 1.5v */
139 bus-width = <8>;
/Documentation/devicetree/bindings/usb/
Dnvidia,tegra194-xusb.yaml79 maxItems: 8
83 maxItems: 8
106 description: PCIe/USB3 analog logic power supply. Must supply 1.05 V.
109 description: High-voltage PCIe/USB3 power supply. Must supply 1.8 V.
112 description: USB controller power supply. Must supply 3.3 V.
115 description: UTMI PLL power supply. Must supply 1.8 V.
118 description: PLLE reference PLL power supply. Must supply 1.05 V.
121 description: PCIe/USB3 PLL power supply. Must supply 1.05 V.
124 description: High-voltage PLLE power supply. Must supply 1.8 V.
/Documentation/gpu/amdgpu/display/
Ddc_pipeline_overview.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
101 id="Arrow2Mend-8"
116 id="Arrow2Mend-8-3"
131 id="Arrow2Mend-8-3-2"
146 id="Arrow2Mend-8-3-2-1"
161 id="Arrow2Mend-8-3-2-7"
166 id="path1200-9-6-9-8"
176 id="Arrow2Mend-8-3-4"
191 id="Arrow2Mend-8-0"
221 id="Arrow2Mend-8-3-2-6"
[all …]
/Documentation/devicetree/bindings/gnss/
Du-blox,neo-6m.yaml23 - u-blox,neo-8
44 v-bckp-supply:
60 compatible = "u-blox,neo-8";
61 v-bckp-supply = <&gnss_v_bckp_reg>;

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