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/Documentation/userspace-api/media/v4l/
Dpixfmt-sdr-pcu18be.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-SDR-FMT-PCU18BE:
9 Planar complex unsigned 18-bit big endian IQ sample
15 number consist of two parts called In-phase and Quadrature (IQ). Both I
16 and Q are represented as a 18 bit unsigned big endian number stored in
17 32 bit space. The remaining unused bits within the 32 bit space will be
20 the 18 bits, bit 17:2 (16 bit) is data and bit 1:0 (2 bit) can be any
26 .. flat-table::
27 :header-rows: 1
28 :stub-columns: 0
[all …]
Dpixfmt-yuv-luma.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _yuv-luma-only:
6 Luma-Only Formats
14 - In all the tables that follow, bit 7 is the most significant bit in a byte.
15 - Formats are described with the minimum number of pixels needed to create a
16 byte-aligned repeating pattern. `...` indicates repetition of the pattern.
17 - Y'\ :sub:`x`\ [9:2] denotes bits 9 to 2 of the Y' value for pixel at column
19 - `0` denotes padding bits set to 0.
28 .. flat-table:: Luma-Only Image Formats
29 :header-rows: 1
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/Documentation/devicetree/bindings/mfd/
Dmc13xxx.txt4 - compatible : Should be "fsl,mc13783" or "fsl,mc13892"
7 - fsl,mc13xxx-uses-adc : Indicate the ADC is being used
8 - fsl,mc13xxx-uses-codec : Indicate the Audio Codec is being used
9 - fsl,mc13xxx-uses-rtc : Indicate the RTC is being used
10 - fsl,mc13xxx-uses-touch : Indicate the touchscreen controller is being used
12 Sub-nodes:
13 - codec: Contain the Audio Codec node.
14 - adc-port: Contain PMIC SSI port number used for ADC.
15 - dac-port: Contain PMIC SSI port number used for DAC.
16 - leds : Contain the led nodes and initial register values in property
[all …]
/Documentation/core-api/
Dpacking.rst6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
15 definitions from the hardware documentation into bit field indices for the
18 (sometimes even 64 bit ones). This creates the inconvenience of having to
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
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/Documentation/devicetree/bindings/timer/
Dnvidia,tegra186-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nvidia,tegra186-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <treding@nvidia.com>
13 The Tegra timer provides 29-bit timer counters and a 32-bit timestamp
16 programmed to generate one-shot, periodic, or watchdog interrupts.
22 - const: nvidia,tegra186-timer
24 The Tegra186 timer provides ten 29-bit timer counters.
25 - const: nvidia,tegra234-timer
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/Documentation/devicetree/bindings/leds/
Dregister-bit-led.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/register-bit-led.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Register Bit LEDs
10 - Linus Walleij <linus.walleij@linaro.org>
13 Register bit leds are used with syscon multifunctional devices where single
14 bits in a certain register can turn on/off a single LED. The register bit LEDs
20 - $ref: /schemas/leds/common.yaml#
25 The unit-address is in the form of @<reg addr>,<bit offset>
[all …]
/Documentation/devicetree/bindings/display/
Dsimple-framebuffer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/simple-framebuffer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hans de Goede <hdegoede@redhat.com>
13 A simple frame-buffer describes a frame-buffer setup by firmware or
19 sub-nodes of the chosen node (*). Simplefb nodes must be named
41 interaction, then the chosen node stdout-path property should point
46 It is advised that devicetree files contain pre-filled, disabled
52 If pre-filled framebuffer nodes are used, the firmware may need
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Dmulti-inno,mi0283qt.txt1 Multi-Inno MI0283QT display panel
4 - compatible: "multi-inno,mi0283qt".
7 all mandatory properties described in ../spi/spi-bus.txt must be specified.
10 - dc-gpios: D/C pin. The presence/absence of this GPIO determines
12 - present: IM=x110 4-wire 8-bit data serial interface
13 - absent: IM=x101 3-wire 9-bit data serial interface
14 - reset-gpios: Reset pin
15 - power-supply: A regulator node for the supply voltage.
16 - backlight: phandle of the backlight device attached to the panel
17 - rotation: panel rotation in degrees counter clockwise (0,90,180,270)
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/Documentation/input/devices/
Dsentelic.rst8 :Copyright: |copy| 2002-2011 Sentelic Corporation.
10 :Last update: Dec-07-2011
27 Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
28 BYTE |---------------|BYTE |---------------|BYTE|---------------|BYTE|---------------|
30 |---------------| |---------------| |---------------| |---------------|
34 Bit5 => Y sign bit
35 Bit4 => X sign bit
40 Byte 2: X Movement(9-bit 2's complement integers)
41 Byte 3: Y Movement(9-bit 2's complement integers)
43 valid values, -8 ~ +7
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/Documentation/devicetree/bindings/edac/
Daspeed-sdram-edac.txt6 The memory controller supports SECDED (single bit error correction, double bit
7 error detection) and single bit error auto scrubbing by reserving 8 bits for
8 every 64 bit word (effectively reducing available memory to 8/9).
14 - compatible: should be one of
15 - "aspeed,ast2400-sdram-edac"
16 - "aspeed,ast2500-sdram-edac"
17 - "aspeed,ast2600-sdram-edac"
18 - reg: sdram controller register set should be <0x1e6e0000 0x174>
19 - interrupts: should be AVIC interrupt #0
25 compatible = "aspeed,ast2500-sdram-edac";
/Documentation/devicetree/bindings/sound/
Dsnps,designware-i2s.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/snps,designware-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jose Abreu <joabreu@synopsys.com>
15 - items:
16 - const: canaan,k210-i2s
17 - const: snps,designware-i2s
18 - enum:
19 - snps,designware-i2s
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/Documentation/devicetree/bindings/i3c/
Di3c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
11 - Miquel Raynal <miquel.raynal@bootlin.com>
20 pattern: "^i3c@[0-9a-f]+$"
22 "#address-cells":
39 "#size-cells":
42 i3c-scl-hz:
49 i2c-scl-hz:
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/Documentation/devicetree/bindings/watchdog/
Dmen-a021-wdt.txt4 - compatible: "men,a021-wdt"
5 - gpios: Specifies the pins that control the Watchdog, order:
7 2: Watchdog fast-mode
9 4: Watchdog reset cause bit 0
10 5: Watchdog reset cause bit 1
11 6: Watchdog reset cause bit 2
14 - None
18 compatible ="men,a021-wdt";
19 gpios = <&gpio3 9 1 /* WD_EN */
/Documentation/devicetree/bindings/display/panel/
Dpanel-mipi-dbi-spi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-mipi-dbi-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Noralf Trønnes <noralf@tronnes.org>
23 - Power:
24 - Vdd: Power supply for display module
25 Called power-supply in this binding.
26 - Vddi: Logic level supply for interface signals
27 Called io-supply in this binding.
[all …]
/Documentation/devicetree/bindings/dma/
Dstericsson,dma40.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
31 9: Synchronous Serial Port SSP1
32 10: Multi-Channel Display Engine MCDE RX
60 38: USB OTG in/out endpoints 1 & 9
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/Documentation/devicetree/bindings/arm/
Darm,juno-fpga-apb-regs.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,juno-fpga-apb-regs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sudeep Holla <sudeep.holla@arm.com>
15 - const: arm,juno-fpga-apb-regs
16 - const: syscon
17 - const: simple-mfd
24 "#address-cells":
27 "#size-cells":
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/Documentation/ABI/testing/
Dsysfs-driver-zynqmp-fpga1 What: /sys/bus/platform/drivers/zynqmp_fpga_manager/firmware:zynqmp-firmware:pcap/status
7 of the FPGA device. Each bit position in the status value is
8 described Below(see ug570 chapter 9).
9 https://docs.xilinx.com/v/u/en-US/ug570-ultrascale-configuration
12 BIT(0) 0: No CRC error
15 BIT(1) 0: Decryptor security not set
18 BIT(2) 0: MMCMs/PLLs are not locked
21 BIT(3) 0: DCI not matched
24 BIT(4) 0: Start-up sequence has not finished
25 1: Start-up sequence has finished
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/Documentation/scsi/
DChangeLog.arcmsr8 ** 1.10.00.08 9/28/2004 Erich Chen modify for x86_64
33 ** 1.20.00.09 9/12/2005 Erich Chen bug fix with abort command handling, firmware versi…
35 ** 1.20.00.10 9/23/2005 Erich Chen enhance sysfs function for change driver's max tag …
40 ** 1.20.00.11 9/29/2005 Erich Chen by comment of Arjan van de Ven fix incorrect msleep…
41 ** cast off sizeof(dma_addr_t) condition for 64bit pci_set_dma_mask
42 ** 1.20.00.12 9/30/2005 Erich Chen bug fix with 64bit platform's ccbs using if over 4G…
43 ** change 64bit pci_set_consistent_dma_mask into 32bit
57 ** 1.implement PCI-Express error recovery function and AER capability
73 ** 2. add readl(reg->iop2drv_doorbell_reg) in arcmsr_handle_hbb_isr()
76 ** 1. modify acb->devstate[i][j]
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/Documentation/devicetree/bindings/regulator/
Dqcom,spmi-regulator.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/qcom,spmi-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Robert Marko <robimarko@gmail.com>
15 - qcom,pm6125-regulators
16 - qcom,pm660-regulators
17 - qcom,pm660l-regulators
18 - qcom,pm8004-regulators
19 - qcom,pm8005-regulators
[all …]
Danatop-regulator.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/anatop-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
13 - $ref: regulator.yaml#
17 const: fsl,anatop-regulator
19 regulator-name: true
21 anatop-reg-offset:
25 anatop-vol-bit-shift:
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/Documentation/devicetree/bindings/crypto/
Dfsl-sec2.txt1 Freescale SoC SEC Security Engines versions 1.x-2.x-3.x
5 - compatible : Should contain entries for this and backward compatible
9 - reg : Offset and length of the register set for the device
10 - interrupts : the SEC's interrupt number
11 - fsl,num-channels : An integer representing the number of channels
13 - fsl,channel-fifo-len : An integer representing the number of
15 - fsl,exec-units-mask : The bitmask representing what execution units
16 (EUs) are available. It's a single 32-bit cell. EU information
20 bit 0 = reserved - should be 0
21 bit 1 = set if SEC has the ARC4 EU (AFEU)
[all …]
/Documentation/admin-guide/mm/
Dsoft-dirty.rst2 Soft-Dirty PTEs
5 The soft-dirty is a bit on a PTE which helps to track which pages a task
8 1. Clear soft-dirty bits from the task's PTEs.
15 3. Read soft-dirty bits from the PTEs.
17 This is done by reading from the ``/proc/PID/pagemap``. The bit 55 of the
18 64-bit qword is the soft-dirty one. If set, the respective PTE was
22 Internally, to do this tracking, the writable bit is cleared from PTEs
23 when the soft-dirty bit is cleared. So, after this, when the task tries to
25 the soft-dirty bit on the respective PTE.
28 soft-dirty bits clear, the #PF-s that occur after that are processed fast.
[all …]
/Documentation/devicetree/bindings/display/bridge/
Danalogix,anx7625.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Xin Ji <xji@analogixsemi.com>
14 The ANX7625 is an ultra-low power 4K Mobile HD Transmitter
28 enable-gpios:
32 reset-gpios:
36 vdd10-supply:
39 vdd18-supply:
42 vdd33-supply:
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/Documentation/hwmon/
Dmax31827.rst1 .. SPDX-License-Identifier: GPL-2.0
12 Addresses scanned: I2C 0x40 - 0x5f
20 Addresses scanned: I2C 0x40 - 0x5f
28 Addresses scanned: I2C 0x40 - 0x5f
34 - Daniel Matyas <daniel.matyas@analog.com>
37 -----------
40 between them is found in the default power-on behaviour of the chips. While the
52 hysteresis value: -40 and -30 degrees for under temperature alarm and +100 and
69 to the operation of the UT status bit.
77 The conversions can be manual with the one-shot functionality and automatic with
[all …]
/Documentation/devicetree/bindings/mailbox/
Dnvidia,tegra186-hsp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
30 - bits 15..8:
31 A bit mask of flags that further specifies the type of shared
33 specified then, 32-bit shared mailbox is used.
34 - bits 7..0:
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