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/Documentation/arch/arm64/
Dasymmetric-32bit.rst2 Asymmetric 32-bit SoCs
7 This document describes the impact of asymmetric 32-bit SoCs on the
8 execution of 32-bit (``AArch32``) applications.
10 Date: 2021-05-17
15 Some Armv9 SoCs suffer from a big.LITTLE misfeature where only a subset
16 of the CPUs are capable of executing 32-bit user applications. On such
17 a system, Linux by default treats the asymmetry as a "mismatch" and
19 ``execve(2)`` of 32-bit ELF binaries, with the latter returning
20 ``-ENOEXEC``. If the mismatch is detected during late onlining of a
21 64-bit-only CPU, then the onlining operation fails and the new CPU is
[all …]
Dbooting.rst12 The AArch64 exception model is made up of a number of exception levels
13 (EL0 - EL3), with EL0, EL1 and EL2 having a secure and a non-secure
20 hypervisor code, or it may just be a handful of instructions for
21 preparing a minimal boot environment.
23 Essentially, the boot loader should provide (as a minimum) the
33 ---------------------------
39 this in a machine dependent manner. (It may use internal algorithms
46 -------------------------
50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
59 ------------------------------
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Dmemory.rst9 tables with a 4KB page size and up to 3 levels with a 64KB page size.
12 with the 4KB page configuration, allowing 39-bit (512GB) or 48-bit
14 64KB pages, only 2 levels of translation tables, allowing 42-bit (4TB)
18 only available when running with a 64KB page size and expands the
21 TTBRx selection is given by bit 55 of the virtual address. The
23 contains only user (non-global) mappings. The swapper_pg_dir address is
27 AArch64 Linux memory layout with 4KB pages + 4 levels (48-bit)::
30 -----------------------------------------------------------------------
44 AArch64 Linux memory layout with 64KB pages + 3 levels (52-bit with HW support)::
47 -----------------------------------------------------------------------
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/Documentation/userspace-api/media/cec/
Dcec-pin-error-inj.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
8 The CEC Pin Framework is a core CEC framework for CEC hardware that only
9 has low-level support for the CEC bus. Most hardware today will have
10 high-level CEC support where the hardware deals with driving the CEC bus,
12 allows you to connect the CEC pin to a GPIO on e.g. a Raspberry Pi and
13 you have now made a CEC adapter.
19 Currently only the cec-gpio driver (when the CEC line is directly
20 connected to a pull-up GPIO line) and the AllWinner A10/A20 drm driver
25 now an ``error-inj`` file.
29 The error injection commands are not a stable ABI and may change in the
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/Documentation/devicetree/bindings/powerpc/
Dibm,powerpc-cpu-features.txt3 (skiboot/doc/device-tree/ibm,powerpc-cpu-features/binding.txt)
9 ibm,powerpc-cpu-features binding
19 /cpus/ibm,powerpc-cpu-features node binding
20 -------------------------------------------
22 Node: ibm,powerpc-cpu-features
26 The node name must be "ibm,powerpc-cpu-features".
28 It is implemented as a child of the node "/cpus", but this must not be
35 - compatible
38 Definition: "ibm,powerpc-cpu-features"
42 be extended in a backward compatible manner which would not warrant a
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/Documentation/devicetree/bindings/dma/stm32/
Dst,stm32-mdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-mdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 MDMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a five-cell specifier for each channel:
14 a phandle to the MDMA controller plus the following five integer cells:
21 3. A 32bit mask specifying the DMA channel configuration
22 -bit 0-1: Source increment mode
26 -bit 2-3: Destination increment mode
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Dst,stm32-dma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The STM32 DMA is a general-purpose direct memory access controller capable of
13 described in the dma.txt file, using a four-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
17 3. A 32bit mask specifying the DMA channel configuration which are device
19 -bit 9: Peripheral Increment Address
22 -bit 10: Memory Increment Address
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/Documentation/i2c/
Dten-bit-addresses.rst2 I2C Ten-bit Addresses
5 The I2C protocol knows about two kinds of device addresses: normal 7 bit
6 addresses, and an extended set of 10 bit addresses. The sets of addresses
7 do not intersect: the 7 bit address 0x10 is not the same as the 10 bit
8 address 0x10 (though a single device could respond to both of them).
9 To avoid ambiguity, the user sees 10 bit addresses mapped to a different
10 address space, namely 0xa000-0xa3ff. The leading 0xa (= 10) represents the
11 10 bit mode. This is used for creating device names in sysfs. It is also
12 needed when instantiating 10 bit devices via the new_device file in sysfs.
14 I2C messages to and from 10-bit address devices have a different format.
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/Documentation/userspace-api/media/rc/
Drc-protos.rst1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
9 IR is encoded as a series of pulses and spaces, using a protocol. These
10 protocols can encode e.g. an address (which device should respond) and a
12 across different devices for a given protocol.
14 Therefore out the output of the IR decoder is a scancode; a single u32
17 Other things can be encoded too. Some IR protocols encode a toggle bit; this
20 toggle bit will invert from one IR message to the next.
22 Some remotes have a pointer-type device which can used to control the
29 rc-5 (RC_PROTO_RC5)
30 -------------------
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/Documentation/staging/
Dcrc32.rst5 A CRC is a long-division remainder. You add the CRC to the message,
6 and the whole thing (message+CRC) is a multiple of the given
10 is used by a lot of hardware implementations, and is why so many
11 protocols put the end-of-frame flag after the CRC.
15 - We're working in binary, so the digits are only 0 and 1, and
16 - When dividing polynomials, there are no carries. Rather than add and
17 subtract, we just xor. Thus, we tend to get a bit sloppy about
21 To produce a 32-bit CRC, the divisor is actually a 33-bit CRC polynomial.
22 Since it's 33 bits long, bit 32 is always going to be set, so usually the
23 CRC is written in hex with the most significant bit omitted. (If you're
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/Documentation/networking/
Doa-tc6-framework.rst1 .. SPDX-License-Identifier: GPL-2.0+
4 OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface (TC6) Framework Support
8 ------------
10 The IEEE 802.3cg project defines two 10 Mbit/s PHYs operating over a
11 single pair of conductors. The 10BASE-T1L (Clause 146) is a long reach
12 PHY supporting full duplex point-to-point operation over 1 km of single
13 balanced pair of conductors. The 10BASE-T1S (Clause 147) is a short reach
14 PHY supporting full / half duplex point-to-point operation over 15 m of
21 works in conjunction with the 10BASE-T1S PHY operating in multidrop mode.
23 The aforementioned PHYs are intended to cover the low-speed / low-cost
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/Documentation/devicetree/bindings/crypto/
Dfsl-sec2.txt1 Freescale SoC SEC Security Engines versions 1.x-2.x-3.x
5 - compatible : Should contain entries for this and backward compatible
9 - reg : Offset and length of the register set for the device
10 - interrupts : the SEC's interrupt number
11 - fsl,num-channels : An integer representing the number of channels
13 - fsl,channel-fifo-len : An integer representing the number of
15 - fsl,exec-units-mask : The bitmask representing what execution units
16 (EUs) are available. It's a single 32-bit cell. EU information
20 bit 0 = reserved - should be 0
21 bit 1 = set if SEC has the ARC4 EU (AFEU)
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/Documentation/driver-api/
Dioctl.rst18 the ioctl system call. While this can be any 32-bit number that uniquely
19 identifies an action for a particular driver, there are a number of
22 ``include/uapi/asm-generic/ioctl.h`` provides four macros for defining
28 The macro name specifies how the argument will be used. It may be a
31 argument or those passing an integer value instead of a pointer.
36 An 8-bit number, often a character literal, specific to a subsystem
37 or driver, and listed in Documentation/userspace-api/ioctl/ioctl-number.rst
40 An 8-bit number identifying the specific command, unique for a give
45 encodes the ``sizeof(data_type)`` value in a 13-bit or 14-bit integer,
46 leading to a limit of 8191 bytes for the maximum size of the argument.
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/Documentation/arch/riscv/
Dvector.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Vector Extension Support for RISC-V Linux
8 order to support the use of the RISC-V Vector Extension.
11 ---------------------
15 these interfaces is to give init systems a way to modify the availability of V
19 are not portable to non-Linux, nor non-RISC-V environments, so it is discourage
20 to use in a portable code. To get the availability of V in an ELF program,
21 please read :c:macro:`COMPAT_HWCAP_ISA_V` bit of :c:macro:`ELF_HWCAP` in the
27 argument consists of two 2-bit enablement statuses and a bit for inheritance
30 Enablement status is a tri-state value each occupying 2-bit of space in
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/Documentation/virt/kvm/x86/
Dmsr.rst1 .. SPDX-License-Identifier: GPL-2.0
4 KVM-specific MSRs
11 Custom MSRs have a range reserved for them, that goes from
16 ---------------
24 4-byte alignment physical address of a memory area which must be
25 in guest RAM. This memory is expected to hold a copy of the following
42 An odd version indicates an in-progress update.
53 Note that although MSRs are per-CPU entities, the effect of this
56 Availability of this MSR must be checked via bit 3 in 0x4000001 cpuid
63 4-byte aligned physical address of a memory area which must be in
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/Documentation/w1/masters/
Dw1-uart.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
4 Kernel driver w1-uart
11 -----------
13 UART 1-Wire bus driver. The driver utilizes the UART interface via the
14 Serial Device Bus to create the 1-Wire timing patterns as described in
15 the document `"Using a UART to Implement a 1-Wire Bus Master"`_.
17 .. _"Using a UART to Implement a 1-Wire Bus Master": https://www.analog.com/en/technical-articles/u…
19 In short, the UART peripheral must support full-duplex and operate in
20 open-drain mode. The timing patterns are generated by a specific
21 combination of baud-rate and transmitted byte, which corresponds to a
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/Documentation/admin-guide/
Dhighuid.rst2 Notes on the change from 16-bit UIDs to 32-bit UIDs
8 - kernel code MUST take into account __kernel_uid_t and __kernel_uid32_t
12 - kernel code should use uid_t and gid_t in kernel-private structures and
15 What's left to be done for 32-bit UIDs on all Linux architectures:
17 - Disk quotas have an interesting limitation that is not related to the
22 properly with huge UIDs. If it can deal with 64-bit file offsets on all
23 architectures, this should not be a problem.
25 - Decide whether or not to keep backwards compatibility with the system
27 (currently, the old 16-bit UID and GID are still written to disk, and
28 part of the former pad space is used to store separate 32-bit UID and
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/Documentation/input/devices/
Delantech.rst4 Copyright (C) 2007-2008 Arjan Opmeer <arjan@opmeer.net>
25 5.2.1 Parity checking and packet re-synchronization
57 combine a status packet with multiple head or motion packets. Hardware version
60 Some Hardware version 3 and version 4 also have a trackpoint which uses a
67 Note that a mouse button is also associated with either the touchpad or the
68 trackpoint when a trackpoint is available. Disabling the Touchpad in xorg
101 Currently a value of "1" will turn on some basic debugging and a value of
107 generate quite a lot of data!
114 non-zero value will turn it ON. For hardware version 1 the default is ON.
118 calculating a parity bit for the last 3 bytes of each packet. The driver
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/Documentation/devicetree/bindings/clock/ti/
Dautoidle.txt3 This binding uses the common clock binding[1]. It assumes a register mapped
5 and a configuration bit setting. Autoidle clock is never an individual
6 clock, it is always a derivative of some basic clock like a gate, divider,
7 or fixed-factor.
9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - reg : offset for the register controlling the autoidle
13 - ti,autoidle-shift : bit shift of the autoidle enable bit
14 - ti,invert-autoidle-bit : autoidle is enabled by setting the bit to 0
18 #clock-cells = <0>;
19 compatible = "ti,divider-clock";
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/Documentation/devicetree/bindings/gpio/
Dgpio-mmio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Bartosz Golaszewski <brgl@bgdev.pl>
14 Some simple GPIO controllers may consist of a single data register or a pair
15 of set/clear-bit registers. Such controllers are common for glue logic in
16 FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped
17 NAND-style parallel busses.
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/Documentation/PCI/endpoint/
Dpci-test-function.rst1 .. SPDX-License-Identifier: GPL-2.0
11 However with the addition of EP-core in linux kernel, it is possible
12 to configure a PCI controller that can operate in EP mode to work as
13 a test device.
15 The PCI endpoint test device is a virtual device (defined in software)
16 used to test the endpoint functionality and serve as a sample driver
33 This register will be used to test BAR0. A known pattern will be written
44 Bit 0 raise legacy IRQ
45 Bit 1 raise MSI IRQ
46 Bit 2 raise MSI-X IRQ
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/Documentation/locking/
Drobust-futex-ABI.rst8 Robust_futexes provide a mechanism that is used in addition to normal
11 The interesting data as to what futexes a thread is holding is kept on a
17 1) a one time call, per thread, to tell the kernel where its list of
22 The existing normal futexes already provide a "Fast Userspace Locking"
23 mechanism, which handles uncontested locking without needing a system
24 call, and handles contested locking by maintaining a list of waiting
26 waiting on a particular futex, and waking up the next waiter on a
29 For robust_futexes to work, the user code (typically in a library such
36 A thread that anticipates possibly using robust_futexes should first
42 The pointer 'head' points to a structure in the threads address space
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/Documentation/bpf/
Dclassic_vs_extended.rst12 - Number of registers increase from 2 to 10:
14 The old format had two registers A and X, and a hidden frame pointer. The
15 new layout extends this to be 10 internal registers and a read-only frame
16 pointer. Since 64-bit CPUs are passing arguments to functions via registers
17 the number of args from eBPF program to in-kernel function is restricted
18 to 5 and one register is used to accept return value from an in-kernel
20 sparcv9/mips64 have 7 - 8 registers for arguments; x86_64 has 6 callee saved
25 64-bit architectures.
27 On 32-bit architectures JIT may map programs that use only 32-bit arithmetic
30 R0 - R5 are scratch registers and eBPF program needs spill/fill them if
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/Documentation/userspace-api/media/dvb/
Dfrontend-stat-properties.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _frontend-stat-properties:
13 stats is supported, and the properties will return a single value for
25 layer, starting from layer A(index 1), layer B (index 2) and so on.
32 - ``svalue`` or ``uvalue``, where ``svalue`` is for signed values of
36 - ``scale`` - Scale for the value. It can be:
38 - ``FE_SCALE_NOT_AVAILABLE`` - The parameter is supported by the
39 frontend, but it was not possible to collect it (could be a
42 - ``FE_SCALE_DECIBEL`` - parameter is a signed value, measured in
45 - ``FE_SCALE_RELATIVE`` - parameter is a unsigned value, where 0
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/Documentation/bpf/standardization/
Dinstruction-set.rst9 referred to as BPF, is a technology with origins in the Linux kernel
10 that can run untrusted programs in a privileged context such as an
14 As a historical note, BPF originally stood for Berkeley Packet Filter,
16 no longer makes sense. BPF is now considered a standalone term that
27 BCP 14 `<https://www.rfc-editor.org/info/rfc2119>`_
28 `<https://www.rfc-editor.org/info/rfc8174>`_
32 of types using a shorthand syntax and refers to several expository,
38 -----
40 a type's signedness (`S`) and bit width (`N`), respectively.
51 .. table:: Meaning of bit-width notation
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