Searched full:apic (Results 1 – 25 of 35) sorted by relevance
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | intel,ce4100-ioapic.yaml | 7 title: Intel I/O Advanced Programmable Interrupt Controller (IO APIC)
13 Intel's Advanced Programmable Interrupt Controller (APIC) is a
14 family of interrupt controllers. The APIC is a split
16 into the processor itself and an external I/O APIC. Local APIC
18 from internal sources and from an external I/O APIC (ioapic).
26 This schema defines bindings for I/O APIC interrupt controller.
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| D | intel,ce4100-lapic.yaml | 13 Intel's Advanced Programmable Interrupt Controller (APIC) is a
14 family of interrupt controllers. The APIC is a split
16 into the processor itself and an external I/O APIC. Local APIC
18 from internal sources and from an external I/O APIC (ioapic).
26 This schema defines bindings for local APIC interrupt controller.
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| /Documentation/arch/x86/i386/ |
| D | IO-APIC.rst | 4 IO-APIC
9 Most (all) Intel-MP compliant SMP boards have the so-called 'IO-APIC',
12 IO-APIC, interrupts from hardware will be delivered only to the
23 If your box boots fine with enabled IO-APIC IRQs, then your
28 0: 1360293 IO-APIC-edge timer
29 1: 4 IO-APIC-edge keyboard
32 14: 1448 IO-APIC-edge ide0
33 16: 28232 IO-APIC-level Intel EtherExpress Pro 10/100 Ethernet
34 17: 51304 IO-APIC-level eth0
97 board does not do default daisy-chaining. (or the IO-APIC has the PIRQ pins
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| D | index.rst | 10 IO-APIC
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| /Documentation/virt/kvm/x86/ |
| D | hypercalls.rst | 99 specifying APIC ID (a1) of the vcpu to be woken up. An additional argument (a0)
147 - a0: lower part of the bitmap of destination APIC IDs
148 - a1: higher part of the bitmap of destination APIC IDs
149 - a2: the lowest APIC ID in bitmap
150 - a3: APIC ICR
156 a0 corresponds to the APIC ID in the third argument (a2), bit 1
157 corresponds to the APIC ID a2+1, and so on.
168 a0: destination APIC ID
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| D | errata.rst | 47 have the same physical APIC ID, KVM will deliver events targeting that APIC ID
50 matching the target APIC ID receive the interrupt).
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| D | msr.rst | 318 injection. Value of 1 means that guest can skip writing EOI to the apic
325 the APIC EOI write anyway.
336 whether it can skip EOI apic write and between guest
359 Bits 0-7: APIC vector for delivery of 'page ready' APF events.
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| D | timekeeping.rst | 269 2.3. APIC
273 as part of the Advanced Programmable Interrupt Controller. The APIC is
277 Although in theory the APIC is a safe and stable source for local interrupts,
279 the APIC CPU-local memory-mapped hardware. Beware that CPU errata may affect
280 the use of the APIC and that workarounds may be required. In addition, some of
285 Since the APIC is documented quite well in the Intel and AMD manuals, we will
286 avoid repetition of the detail here. It should be pointed out that the APIC
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| /Documentation/devicetree/bindings/x86/ |
| D | ce4100.txt | 6 Many of the "generic" devices like HPET or IO APIC have the ce4100
38 Local APIC ID, the unique number assigned to each processor by
52 If the OS is using the IO-APIC for interrupt routing then the reported
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| /Documentation/PCI/ |
| D | boot-interrupts.rst | 13 interrupt messages (Assert_INTx/Deassert_INTx). The integrated IO-APIC in a
15 MSI interrupts. If the IO-APIC is disabled (via the mask bits in the
16 IO-APIC table entries), the messages are routed to the legacy PCH. This
18 did not support the IO-APIC and for boot. Intel in the past has used the
80 devices. IO-APIC is only in the PCH. Devices connected to the Core IO's
105 PCH - they are either converted into MSI via the integrated IO-APIC
106 (if the IO-APIC mask bit is clear in the appropriate entries)
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| /Documentation/arch/x86/x86_64/ |
| D | boot-options.rst | 72 apic
73 Use IO-APIC. Default
76 Don't use the IO-APIC.
79 Don't use the local APIC
82 Don't use the local APIC (alias for i386 compatibility)
85 See Documentation/arch/x86/i386/IO-APIC.rst
88 Don't set up the APIC timer
91 Don't check the IO-APIC timer. This can work around
95 Do APIC timer calibration using the pmtimer. Implies
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| /Documentation/translations/zh_CN/core-api/irq/ |
| D | irq-affinity.rst | 47 … 1785 1785 1783 0 0 0 0 IO-APIC-level eth1
65 … 1785 1785 1783 1784 1069 1070 1069 IO-APIC-level eth1
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| D | irq-domain.rst | 185 Device --> IOAPIC -> Interrupt remapping Controller -> Local APIC -> CPU
191 3) Local APIC 控制器
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| /Documentation/core-api/irq/ |
| D | irq-affinity.rst | 39 … 1785 1785 1783 0 0 0 0 IO-APIC-level eth1
58 … 1785 1785 1783 1784 1069 1070 1069 IO-APIC-level eth1
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| D | irq-domain.rst | 222 Device --> IOAPIC -> Interrupt remapping Controller -> Local APIC -> CPU
228 3) Local APIC controller
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| /Documentation/power/ |
| D | tricks.rst | 12 * turn off APIC and preempt
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| /Documentation/arch/x86/ |
| D | intel-hfi.rst | 47 Local Vector Table of a CPU's local APIC, there exists a register for the
62 thermal entry in the Local APIC's Local Vector Table.
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| D | topology.rst | 69 and deduced from the APIC IDs of the cores in the package.
88 - On Intel, the first APIC ID of the list of CPUs sharing the Last Level
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| D | entry_64.rst | 39 - APIC interrupts: Various special-purpose interrupts for things
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| /Documentation/virt/hyperv/ |
| D | clocks.rst | 34 APIC timer, and RTC. Hyper-V does not provide a virtualized HPET in
78 virtualized PIT and local APIC timer also work, but Hyper-V stimer0
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| /Documentation/firmware-guide/acpi/apei/ |
| D | einj.rst | 86 Processor APIC field valid (see param3 below).
110 Used when the 0x1 bit is set in "flags" to specify the APIC id
203 [22715.834759] EDAC sbridge MC3: PROCESSOR 0:306e7 TIME 1422553404 SOCKET 0 APIC 0
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| /Documentation/admin-guide/ |
| D | kernel-parameters.rst | 101 APIC APIC support is enabled.
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| D | kernel-parameters.txt | 35 2: use 2nd APIC table, if available
36 1,0: use 1st APIC table
111 default in APIC mode
358 vapic - Use virtual APIC mode, which allows IOMMU
408 apic= [APIC,X86,EARLY] Advanced Programmable Interrupt Controller
412 when initialising the APIC and IO-APIC components.
413 For X86-32, this can also be used to specify an APIC
415 Format: apic=driver_name
416 Examples: apic=bigsmp
418 apic_extnmi= [APIC,X86,EARLY] External NMI delivery setting
[all …]
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| /Documentation/filesystems/ |
| D | proc.rst | 787 0: 1243498 1214548 IO-APIC-edge timer
788 1: 8949 8958 IO-APIC-edge keyboard
790 5: 11286 10161 IO-APIC-edge soundblaster
791 8: 1 0 IO-APIC-edge rtc
792 9: 27422 27407 IO-APIC-edge 3c503
793 12: 113645 113873 IO-APIC-edge PS/2 Mouse
795 14: 22491 24012 IO-APIC-edge ide0
796 15: 2183 2415 IO-APIC-edge ide1
797 17: 30564 30414 IO-APIC-level eth0
798 18: 177 164 IO-APIC-level bttv
[all …]
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| /Documentation/virt/ |
| D | ne_overview.rst | 61 APIC and IOAPIC - to get interrupts from virtio-vsock device. The virtio-mmio
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