Searched full:armv8 (Results 1 – 25 of 42) sorted by relevance
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| /Documentation/devicetree/bindings/ |
| D | numa.txt | 176 compatible = "arm,armv8";
184 compatible = "arm,armv8";
191 compatible = "arm,armv8";
198 compatible = "arm,armv8";
205 compatible = "arm,armv8";
212 compatible = "arm,armv8";
219 compatible = "arm,armv8";
226 compatible = "arm,armv8";
233 compatible = "arm,armv8";
241 compatible = "arm,armv8";
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| /Documentation/devicetree/bindings/perf/ |
| D | spe-pmu.yaml | 7 title: ARMv8.2 Statistical Profiling Extension (SPE) Performance Monitor Units (PMU)
13 ARMv8.2 introduces the optional Statistical Profiling Extension for collecting
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| /Documentation/trace/coresight/ |
| D | coresight-cpu-debug.rst | 11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
49 - ARMv8-a (ARM DDI 0487A.k) and ARMv7-a (ARM DDI 0406C.b) have different
52 If PCSROffset=0b0000, on ARMv8-a the feature of EDPCSR is not implemented;
59 If PCSROffset=0b0010, ARMv8-a defines "EDPCSR implemented, and samples have
61 state". So on ARMv8 if EDDEVID1.PCSROffset is 0b0010 and the CPU operates
70 have been enabled properly. In ARMv8-a ARM (ARM DDI 0487A.k) chapter 'H9.1
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| /Documentation/devicetree/bindings/power/reset/ |
| D | ocelot-reset.txt | 7 microchip Sparx5 armv8 SoC's.
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| /Documentation/devicetree/bindings/arm/nuvoton/ |
| D | nuvoton,ma35d1.yaml | 13 Boards with an ARMv8 based Nuvoton MA35 series SoC shall have
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| /Documentation/devicetree/bindings/timer/ |
| D | arm,arch_timer.yaml | 30 - arm,armv8-timer
32 - const: arm,armv8-timer
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| /Documentation/virt/hyperv/ |
| D | clocks.rst | 8 On arm64, Hyper-V virtualizes the ARMv8 architectural system counter
16 of Hyper-V for arm64 only partially virtualize the ARMv8
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| /Documentation/arch/arm64/ |
| D | sve.rst | 473 ARMv8-A programmer's model that are relevant to this document.
484 For each Zn, Zn bits [127:0] alias the ARMv8-A vector register Vn.
508 * FPSR and FPCR are retained from ARMv8-A, and interact with SVE floating-point
509 operations in a similar way to the way in which they interact with ARMv8
543 The ARMv8-A base procedure call standard is extended as follows with respect to
554 Appendix B. ARMv8-A FP/SIMD programmer's model
562 ARMv8-A defines the following floating-point / SIMD register state:
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| D | memory.rst | 17 ARMv8.2 adds optional support for Large Virtual Address space. This is
103 If the ARMv8.2-LVA optional feature is present, and we are running
144 To maintain compatibility with software that relies on the ARMv8.0
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| D | memory-tagging-extension.rst | 16 ARMv8.5 based processors introduce the Memory Tagging Extension (MTE)
17 feature. MTE is built on top of the ARMv8.0 virtual address tagging TBI
258 * To be compiled with -march=armv8.5-a+memtag
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| D | perf.rst | 111 The focus is set on the armv8 PMUv3 which makes sure that the access to the pmu
174 FEAT_PMUv3_TH (Armv8.8) permits a PMU counter to increment only on
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| D | amu.rst | 19 ARMv8.4 CPU architecture.
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| D | acpi_object_usage.rst | 28 Table Usage for ARMv8 Linux
511 Name Section Usage for ARMv8 Linux
707 Further, it is essential that the ARMv8 SoC provide a fully functional
726 APEI requires the equivalent of an SCI and an NMI on ARMv8. The SCI is used
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| D | pointer-authentication.rst | 16 The ARMv8.3 Pointer Authentication extension adds primitives that can be
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| /Documentation/translations/zh_CN/arch/arm64/ |
| D | amu.rst | 21 活动监控是 ARMv8.4 CPU 架构引入的一个可选扩展特性。
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| D | booting.txt | 174 *译者注：对于 PoC 以及缓存相关内容，请参考 ARMv8 构架参考手册
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| /Documentation/devicetree/bindings/arm/ |
| D | microchip,sparx5.yaml | 13 The Microchip Sparx5 SoC is a ARMv8-based used in a family of
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| D | arm,coresight-cpu-debug.yaml | 16 CoreSight CPU debug component are compliant with the ARMv8 architecture
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| D | pmu.yaml | 27 - arm,armv8-pmuv3 # Only for s/w models
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| /Documentation/translations/zh_TW/arch/arm64/ |
| D | amu.rst | 24 活動監控是 ARMv8.4 CPU 架構引入的一個可選擴展特性。
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| D | booting.txt | 178 *譯者注：對於 PoC 以及緩存相關內容，請參考 ARMv8 構架參考手冊
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| /Documentation/driver-api/firmware/ |
| D | other_interfaces.rst | 26 FPGA programming. In terms of the ARMv8 architecture, the kernel runs
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| /Documentation/translations/zh_CN/scheduler/ |
| D | schedutil.rst | 62 ARMv8.4-AMU）来计算这一比率。具体到Intel，我们使用::
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| /Documentation/virt/kvm/arm/ |
| D | pkvm.rst | 10 translation capability of the Armv8 MMU to isolate guest memory from the host
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| /Documentation/virt/kvm/devices/ |
| D | vcpu.rst | 95 architecture (10 bits on ARMv8.0, 16 bits from ARMv8.1 onwards).
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