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/Documentation/devicetree/bindings/cache/
Dandestech,ax45mp-cache.yaml5 $id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#
8 title: Andestech AX45MP L2 Cache Controller
23 - andestech,ax45mp-cache
31 - const: andestech,ax45mp-cache
73 compatible = "andestech,ax45mp-cache", "cache";
/Documentation/devicetree/bindings/interrupt-controller/
Dsifive,plic-1.0.0.yaml36 RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
/Documentation/devicetree/bindings/riscv/
Dcpus.yaml36 - andestech,ax45mp
Dextensions.yaml570 Registers in the AX45MP datasheet.
571 https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf