| /Documentation/devicetree/bindings/dma/ |
| D | snps,dw-axi-dmac.yaml | 4 $id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
7 title: Synopsys DesignWare AXI DMA Controller
13 Synopsys DesignWare AXI DMA Controller DT Binding
21 - snps,axi-dma-1.01a
22 - intel,kmb-axi-dma
23 - starfive,jh7110-axi-dma
24 - starfive,jh8100-axi-dma
68 Number of AXI masters supported by the hardware.
74 AXI data width supported by hardware.
93 snps,axi-max-burst-len:
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| D | adi,axi-dmac.txt | 1 Analog Devices AXI-DMAC DMA controller
4 - compatible: Must be "adi,axi-dmac-1.00.a".
7 - clocks: Phandle and specifier to the controllers AXI interface clock
26 0 (AXI_DMAC_TYPE_AXI_MM): Memory mapped AXI interface
27 1 (AXI_DMAC_TYPE_AXI_STREAM): Streaming AXI interface
36 DMA clients connected to the AXI-DMAC DMA controller must use the format
43 compatible = "adi,axi-dmac-1.00.a";
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| /Documentation/devicetree/bindings/dma/xilinx/ |
| D | xilinx_dma.txt | 1 Xilinx AXI VDMA engine, it does transfers between memory and video devices.
6 Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
14 Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream
20 "xlnx,axi-vdma-1.00.a"
21 "xlnx,axi-dma-1.00.a"
22 "xlnx,axi-cdma-1.00.a"
23 "xlnx,axi-mcdma-1.00.a"
47 Optional properties for AXI DMA and MCDMA:
53 Optional properties for AXI DMA:
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| /Documentation/devicetree/bindings/clock/ |
| D | allwinner,sun4i-a10-axi-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-axi-clk.yaml#
7 title: Allwinner A10 AXI Clock
21 - allwinner,sun4i-a10-axi-clk
22 - allwinner,sun8i-a23-axi-clk
44 axi@1c20054 {
46 compatible = "allwinner,sun4i-a10-axi-clk";
49 clock-output-names = "axi";
55 compatible = "allwinner,sun8i-a23-axi-clk";
58 clock-output-names = "axi";
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| D | adi,axi-clkgen.yaml | 4 $id: http://devicetree.org/schemas/clock/adi,axi-clkgen.yaml#
7 title: Analog Devices AXI clkgen pcore clock generator
22 - adi,axi-clkgen-2.00.a
23 - adi,zynqmp-axi-clkgen-2.00.a
30 clock is the AXI bus clock that needs to be enabled so we can access the
63 compatible = "adi,axi-clkgen-2.00.a";
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| D | baikal,bt1-ccu-div.yaml | 26 3) AXI-bus clock dividers (AXI) - described in this binding file.
38 +----+ | | | +-|AXI|-|- AXI-bus
52 domain (like AXI-bus or System Device consumers). The dividers have the
78 Similarly the dividers with output clocks utilized as AXI-bus reference clocks
79 are called AXI-bus CCU. Both of them use the common clock bindings with no
82 'include/dt-bindings/reset/bt1-ccu.h'. Since System Devices and AXI-bus CCU
90 const: baikal,bt1-ccu-axi
125 - baikal,bt1-ccu-axi
154 # AXI-bus Clock Control Unit node:
159 compatible = "baikal,bt1-ccu-axi";
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| /Documentation/devicetree/bindings/sound/ |
| D | adi,axi-spdif-tx.txt | 1 ADI AXI-SPDIF controller
4 - compatible : Must be "adi,axi-spdif-tx-1.00.a"
7 The controller expects two clocks, the clock used for the AXI interface and
9 - clock-names: "axi" for the clock to the AXI interface, "ref" for the sample
24 compatible = "adi,axi-spdif-tx-1.00.a";
27 clock-names = "axi", "ref";
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| D | adi,axi-i2s.txt | 1 ADI AXI-I2S controller
7 - compatible : Must be "adi,axi-i2s-1.00.a"
10 The controller expects two clocks, the clock used for the AXI interface and
12 - clock-names : "axi" for the clock to the AXI interface, "ref" for the sample
28 compatible = "adi,axi-i2s-1.00.a";
31 clock-names = "axi", "ref";
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| /Documentation/devicetree/bindings/pwm/ |
| D | adi,axi-pwmgen.yaml | 4 $id: http://devicetree.org/schemas/pwm/adi,axi-pwmgen.yaml#
7 title: Analog Devices AXI PWM generator
14 The Analog Devices AXI PWM generator can generate PWM signals
24 const: adi,axi-pwmgen-2.00.a
39 - const: axi
52 compatible = "adi,axi-pwmgen-2.00.a";
55 clock-names = "axi", "ext";
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| /Documentation/devicetree/bindings/bus/ |
| D | baikal,bt1-axi.yaml | 5 $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
8 title: Baikal-T1 AXI-bus
16 cores. Traffic arbitration is done by means of DW AXI Interconnect (so
17 called AXI Main Interconnect) routing IO requests from one block to
21 an IRQ is raised and a faulty situation is reported to the AXI EHB
22 (Errors Handler Block) embedded on top of the DW AXI Interconnect and
31 const: baikal,bt1-axi
36 - description: Synopsys DesignWare AXI Interconnect QoS registers
37 - description: AXI EHB MMIO system controller registers
87 compatible = "baikal,bt1-axi", "simple-bus";
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| D | brcm,bus-axi.txt | 1 Driver for ARM AXI Bus with Broadcom Plugins (bcma)
5 - compatible : brcm,bus-axi
9 The cores on the AXI bus are automatically detected by bcma with the
17 The top-level axi bus may contain children representing attached cores
24 axi@18000000 {
25 compatible = "brcm,bus-axi";
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| /Documentation/devicetree/bindings/hwmon/ |
| D | adi,axi-fan-control.yaml | 5 $id: http://devicetree.org/schemas/hwmon/adi,axi-fan-control.yaml#
8 title: Analog Devices AXI FAN Control
14 Bindings for the Analog Devices AXI FAN Control driver. Specifications of the
22 - adi,axi-fan-control-1.00.a
51 fpga_axi: fpga-axi {
55 axi_fan_control: axi-fan-control@80000000 {
56 compatible = "adi,axi-fan-control-1.00.a";
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| /Documentation/devicetree/bindings/pci/ |
| D | qcom,pcie.yaml | 250 - const: axi # AXI reset
275 - const: master_bus # Master AXI clock
276 - const: slave_bus # Slave AXI clock
298 - const: master_bus # Master AXI clock
299 - const: slave_bus # Slave AXI clock
305 - const: axi_m # AXI master reset
306 - const: axi_s # AXI slave reset
312 - const: axi_m_sticky # AXI sticky reset
334 - const: bus_master # Master AXI clock
335 - const: bus_slave # Slave AXI clock
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| D | qcom,pcie-ep.yaml | 145 - description: PCIe Master AXI clock
146 - description: PCIe Slave AXI clock
147 - description: PCIe Slave Q2A AXI clock
180 - description: PCIe Master AXI clock
181 - description: PCIe Slave AXI clock
182 - description: PCIe Slave Q2A AXI clock
185 - description: PCIe AGGRE NOC AXI clock
219 - description: PCIe Master AXI clock
220 - description: PCIe Slave AXI clock
221 - description: PCIe Slave Q2A AXI clock
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| /Documentation/devicetree/bindings/fpga/ |
| D | xlnx,pr-decoupler.yaml | 7 title: Xilinx LogiCORE Partial Reconfig Decoupler/AXI shutdown manager Softcore
21 Xilinx LogiCORE Dynamic Function eXchange(DFX) AXI shutdown manager Softcore
23 eXchange AXI shutdown manager prevents AXI traffic from passing through the
26 preventing the system deadlock that can occur if AXI transactions are
38 - const: xlnx,dfx-axi-shutdown-manager-1.00
39 - const: xlnx,dfx-axi-shutdown-manager
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| /Documentation/devicetree/bindings/net/ |
| D | xlnx,axi-ethernet.yaml | 4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
7 title: AXI 1G/2.5G Ethernet Subsystem
10 Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
16 Management configuration is done through the AXI interface, while payload is
17 sent and received through means of an AXI DMA controller. This driver
18 includes the DMA driver code, so this driver is incompatible with AXI DMA
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
34 and length of the AXI DMA controller IO space, unless
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | adi,axi-adc.yaml | 4 $id: http://devicetree.org/schemas/iio/adc/adi,axi-adc.yaml#
7 title: Analog Devices AXI ADC IP core
13 Analog Devices Generic AXI ADC IP core for interfacing an ADC device
26 - adi,axi-adc-10.0.a
60 axi-adc@44a00000 {
61 compatible = "adi,axi-adc-10.0.a";
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| D | xilinx-xadc.txt | 10 on all series 7 platforms and is a softmacro with a AXI interface. This binding
17 System Monitor through an AXI interface in the FPGA fabric. This IP core is
25 * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
33 when using the axi-xadc or the axi-system-management-wizard this must be
34 the clock that provides the clock to the AXI bus interface of the core.
110 compatible = "xlnx,axi-xadc-1.00.a";
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| /Documentation/devicetree/bindings/spi/ |
| D | adi,axi-spi-engine.yaml | 4 $id: http://devicetree.org/schemas/spi/adi,axi-spi-engine.yaml#
7 title: Analog Devices AXI SPI Engine Controller
10 The AXI SPI Engine controller is part of the SPI Engine framework[1] and
26 const: adi,axi-spi-engine-1.00.a
36 - description: The AXI interconnect clock.
56 compatible = "adi,axi-spi-engine-1.00.a";
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| /Documentation/devicetree/bindings/iio/dac/ |
| D | adi,axi-dac.yaml | 4 $id: http://devicetree.org/schemas/iio/dac/adi,axi-dac.yaml#
7 title: Analog Devices AXI DAC IP core
13 Analog Devices Generic AXI DAC IP core for interfacing a DAC device
26 - adi,axi-dac-9.1.b
55 compatible = "adi,axi-dac-9.1.b";
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| /Documentation/devicetree/bindings/w1/ |
| D | amd,axi-1wire-host.yaml | 4 $id: http://devicetree.org/schemas/w1/amd,axi-1wire-host.yaml#
7 title: AMD AXI 1-wire bus host for programmable logic
14 const: amd,axi-1wire-host
38 compatible = "amd,axi-1wire-host";
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| /Documentation/admin-guide/perf/ |
| D | imx-ddr.rst | 17 (AXI filter setting) fields of the perf_event_attr structure, see /sys/bus/event_source/
28 AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write)
32 type of AXI filter (filter, enhanced_filter and super_filter). Value 0 for
49 This filter doesn't support filter different AXI ID for axid-read and axid-write
73 There is a limitation in previous AXI filter, it cannot filter different IDs
75 extension of AXI ID filter. One improvement is that counter 1-3 has their own
77 improvement is that counter 1-3 supports AXI PORT and CHANNEL selection. Support
82 --Counter N MUX CNTL register - including AXI CHANNEL and AXI PORT.
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| /Documentation/devicetree/bindings/usb/ |
| D | starfive,jh7110-usb.yaml | 42 - description: AXI clock
50 - const: axi
57 - description: AXI clock reset
64 - const: axi
97 clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
102 reset-names = "pwrup", "apb", "axi", "utmi_apb";
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| /Documentation/devicetree/bindings/interconnect/ |
| D | qcom,sm8450-rpmh.yaml | 70 - description: aggre UFS PHY AXI clock
71 - description: aggre USB3 PRIM AXI clock
83 - description: aggre-NOC PCIe 0 AXI clock
84 - description: aggre-NOC PCIe 1 AXI clock
85 - description: aggre UFS PHY AXI clock
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| /Documentation/devicetree/bindings/display/msm/ |
| D | gmu.yaml | 112 - description: GPU AXI clock
118 - const: axi
144 - description: GPU AXI clock
153 - const: axi
213 - description: GPU AXI clock
220 - const: axi
249 - description: GPU AXI clock
258 - const: axi
307 clock-names = "gmu", "cxo", "axi", "memnoc";
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