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/Documentation/devicetree/bindings/misc/
Dxlnx,sd-fec.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/misc/xlnx,sd-fec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cvetic, Dragan <dragan.cvetic@amd.com>
11 - Erim, Salih <salih.erim@amd.com>
15 which provides high-throughput LDPC and Turbo Code implementations.
17 customer specified Quasi-cyclic (QC) codes. The Turbo decode functionality
23 const: xlnx,sd-fec-1.1
33 - description: Main processing clock for processing core
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/Documentation/devicetree/bindings/fpga/
Dxlnx,pr-decoupler.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,pr-decoupler.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
13 - $ref: fpga-bridge.yaml#
22 is compatible with the Xilinx LogiCORE pr-decoupler. The Dynamic Function
24 bridge. The controller safely handles AXI4MM and AXI4-Lite interfaces on a
28 Please refer to fpga-region.txt and fpga-bridge.txt in this directory for
34 - items:
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/Documentation/devicetree/bindings/media/
Dallegro,al5e.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Tretter <m.tretter@pengutronix.de>
12 description: |-
23 - items:
24 - const: allegro,al5e-1.1
25 - const: allegro,al5e
26 - items:
27 - const: allegro,al5d-1.1
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/Documentation/devicetree/bindings/media/xilinx/
Dxlnx,csi2rxss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx MIPI CSI-2 Receiver Subsystem
10 - Vishal Sagar <vishal.sagar@amd.com>
13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
14 traffic from compliant camera sensors and send the output as AXI4 Stream
16 The subsystem consists of a MIPI D-PHY in slave mode which captures the
17 data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the
19 AXI4 Stream video data.
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/Documentation/devicetree/bindings/gpio/
Dxlnx,gpio-xilinx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/xlnx,gpio-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neeli Srinivas <srinivas.neeli@amd.com>
14 to an AXI4-Lite interface. The AXI GPIO can be configured as either
15 a single or a dual-channel device. The width of each channel is
22 - xlnx,xps-gpio-1.00.a
27 "#gpio-cells":
33 gpio-controller: true
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/Documentation/networking/device_drivers/can/ctu/
Dctucanfd-driver.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
10 ------------------------
19 `Vivado integration <https://gitlab.fel.cvut.cz/canbus/zynq/zynq-can-sja1000-top>`_
20 and Intel Cyclone V 5CSEMA4U23C6 based DE0-Nano-SoC Terasic board
21 `QSys integration <https://gitlab.fel.cvut.cz/canbus/intel-soc-ctucanfd>`_
23 `PCIe integration <https://gitlab.fel.cvut.cz/canbus/pcie-ctucanfd>`_ of the core.
33 version of emulation support can be cloned from ctu-canfd branch of QEMU local
34 development `repository <https://gitlab.fel.cvut.cz/canbus/qemu-canbus>`_.
38 ---------------
59 it allows for device hot-plug.
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