| /Documentation/devicetree/bindings/crypto/ |
| D | img-hash.txt | 1 Imagination Technologies hardware hash accelerator
3 The hash accelerator provides hardware hashing acceleration for
8 - compatible : "img,hash-accelerator"
15 "hash" Used to clock data through the accelerator
20 compatible = "img,hash-accelerator";
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| D | xlnx,zynqmp-aes.yaml | 7 title: Xilinx ZynqMP AES-GCM Hardware Accelerator
14 The ZynqMP AES-GCM hardened cryptographic accelerator is used to
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| D | mv_cesa.txt | 1 Marvell Cryptographic Engines And Security Accelerator
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| D | aspeed,ast2500-hace.yaml | 7 title: ASPEED HACE hash and crypto Hardware Accelerator Engines
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| D | aspeed,ast2600-acry.yaml | 7 title: ASPEED ACRY ECDSA/RSA Hardware Accelerator Engines
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| /Documentation/devicetree/bindings/dma/ |
| D | stericsson,dma40.yaml | 70 48: Crypto Accelerator 1
71 49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX
72 50: Hash Accelerator 1 TX
83 61: Crypto Accelerator 0
84 62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX
85 63: Hash Accelerator 0 TX
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| /Documentation/devicetree/bindings/mfd/ |
| D | stericsson,db8500-prcmu.yaml | 123 description: Smart Video Accelerator (SVA) multimedia DSP (MMDSP)
124 voltage regulator. This is the voltage for the accelerator DSP
131 description: Smart Video Accelerator (SVA) multimedia DSP (MMDSP)
138 description: Smart Video Accelerator (SVA) multimedia DSP (MMDSP)
145 description: Smart Image Accelerator (SIA) multimedia DSP (MMDSP)
146 voltage regulator. This is the voltage for the accelerator DSP
153 description: Smart Image Accelerator (SIA) multimedia DSP (MMDSP)
160 description: Smart Image Accelerator (SIA) multimedia DSP (MMDSP)
167 description: Smart Graphics Accelerator (SGA) voltage regulator.
169 accelerator block.
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| /Documentation/devicetree/bindings/powerpc/4xx/ |
| D | ppc440spe-adma.txt | 1 PPC440SPe DMA/XOR (DMA Controller and XOR Accelerator)
60 iii) XOR Accelerator node
64 - compatible : "amcc,xor-accelerator";
71 compatible = "amcc,xor-accelerator";
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| /Documentation/devicetree/bindings/arm/omap/ |
| D | iva.txt | 1 * TI - IVA (Imaging and Video Accelerator) subsystem
3 The IVA contain various audio, video or imaging HW accelerator
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| /Documentation/misc-devices/ |
| D | uacce.rst | 6 Uacce (Unified/User-space-access-intended Accelerator Framework) targets to
8 So accelerator can access any data structure of the main cpu.
13 Uacce takes the hardware accelerator as a heterogeneous processor, while
21 | User application (CPU) | | Hardware Accelerator |
95 The accelerator device present itself as an Uacce object, which exports as
175 match the right accelerator accordingly.
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| /Documentation/devicetree/bindings/media/ |
| D | st,stm32-dma2d.yaml | 7 title: STMicroelectronics STM32 Chrom-Art Accelerator DMA2D
10 Chrom-ART Accelerator(DMA2D), graphical hardware accelerator
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| D | microchip,sama5d4-vdec.yaml | 14 Hantro G1 video decode accelerator present on Microchip SAMA5D4 SoCs.
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| D | qcom,venus-common.yaml | 14 The Venus IP is a video encode and decode accelerator present
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| /Documentation/accel/ |
| D | introduction.rst | 16 Typically, a compute accelerator will belong to one of the following
54 devices. In addition, new features that will be added for the accelerator
61 from trying to use an accelerator as a GPU, the compute accelerators will be
67 The accelerator devices will be exposed to the user space with the dedicated
85 To expose your device as an accelerator, two changes are needed to
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| /Documentation/arch/powerpc/ |
| D | cxl.rst | 2 Coherent Accelerator Interface (CXL)
8 The coherent accelerator interface is designed to allow the
11 Accelerator Interface Architecture (CAIA).
13 IBM refers to this as the Coherent Accelerator Processor Interface
17 Coherent in this context means that the accelerator and CPUs can
46 The POWER Service Layer (PSL) and the Accelerator Function Unit
52 The AFU is the core part of the accelerator (eg. the compression,
86 this mode, only one userspace process can use the accelerator at
91 applications may use the accelerator (although specific AFUs may
102 A portion of the accelerator MMIO space can be directly mapped
[all …]
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| D | vas-api.rst | 5 Virtual Accelerator Switchboard (VAS) userspace API
11 Power9 processor introduced Virtual Accelerator Switchboard (VAS) which
13 (hardware accelerator) referred to as the Nest Accelerator (NX). The NX
31 requests directly to NX accelerator.
82 accelerator. It finds CPU on which the user process is executing and
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | k3-ringacc.yaml | 8 title: Texas Instruments K3 NavigatorSS Ring Accelerator
15 The Ring Accelerator (RA) is a machine which converts read/write accesses
25 The Ring Accelerator is a hardware module that is responsible for accelerating
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| /Documentation/accel/qaic/ |
| D | index.rst | 8 accelerator cards.
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| /Documentation/driver-api/crypto/iaa/ |
| D | index.rst | 4 IAA (Intel Analytics Accelerator)
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| /Documentation/ABI/testing/ |
| D | sysfs-driver-hid-logitech-lg4ff | 72 Description: Controls whether a combined value of accelerator and brake is
74 which can do not work with separate accelerator/brake axis.
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| /Documentation/devicetree/bindings/net/ |
| D | keystone-netcp.txt | 4 The network coprocessor (NetCP) is a hardware accelerator that processes
7 accelerator (PA) module to perform packet classification operations such as
9 generation. NetCP can also optionally include a Security Accelerator (SA)
31 | |-> Packet Accelerator
33 | |-> Security Accelerator
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| D | hisilicon-hns-nic.txt | 7 - ae-handle: accelerator engine handle for hns,
10 - port-id: is the index of port provided by DSAF (the accelerator). DSAF can
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| /Documentation/translations/zh_CN/ |
| D | glossary.rst | 29 * OpenCAPI: 开放相干加速器处理器接口。（Open Coherent Accelerator Processor Interface）
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| /Documentation/devicetree/bindings/powerpc/ |
| D | ibm,vas.txt | 1 * IBM Powerpc Virtual Accelerator Switchboard (VAS)
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| /Documentation/driver-api/cxl/ |
| D | maturity-map.rst | 165 Accelerator section in Feature and Capabilities
168 * [0] Accelerator memory enumeration HDM-D (CXL 1.1/2.0 Type-2)
169 * [0] Accelerator memory enumeration HDM-DB (CXL 3.0 Type-2)
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