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/Documentation/devicetree/bindings/regulator/
Dti-abb-regulator.txt9 - reg: Address and length of the register set for the device. It contains
12 - "base-address" - contains base address of ABB module (ti,abb-v1,ti,abb-v2)
13 - "control-address" - contains control register address of ABB module (ti,abb-v3)
14 - "setup-address" - contains setup register address of ABB module (ti,abb-v3)
15 - "int-address" - contains address of interrupt register for ABB module
17 - #address-cells: should be 0
47 - "efuse-address" - Contains efuse base address used to pick up ABB info.
48 - "ldo-address" - Contains address of ABB LDO override register.
49 "efuse-address" is required for this.
50 - ti,ldovbb-vset-mask - Required if ldo-address is set, mask for LDO override
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/Documentation/arch/x86/x86_64/
D5level-paging.rst9 Original x86-64 was limited by 4-level paging to 256 TiB of virtual address
10 space and 64 TiB of physical address space. We are already bumping into
17 It bumps the limits to 128 PiB of virtual address space and 4 PiB of
18 physical address space. This "ought to be enough for anybody" ©.
34 User-space and large virtual address space
36 On x86, 5-level paging enables 56-bit userspace virtual address space.
42 To mitigate this, we are not going to allocate virtual address space
45 But userspace can ask for allocation from full address space by
46 specifying hint address (with or without MAP_FIXED) above 47-bits.
48 If hint address set above 47-bit, but MAP_FIXED is not specified, we try
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Dfsgs.rst8 notation is used to address a byte within a segment:
10 Segment-register:Byte-address
12 The segment base address is added to the Byte-address to compute the
13 resulting virtual address which is accessed. This allows to access multiple
14 instances of data with the identical Byte-address, i.e. the same code. The
15 selection of a particular instance is purely based on the base-address in
19 limits. The limits can be used to enforce address space protections.
21 In 64-bit mode the CS/SS/DS/ES segments are ignored and the base address is
22 always 0 to provide a full 64bit address space. The FS and GS segments are
28 The FS segment is commonly used to address Thread Local Storage (TLS). FS
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/Documentation/arch/arm/
Dporting.rst12 virtual address to a physical address. Normally, it is simply:
21 Start address of decompressor. There's no point in talking about
24 the kernel at this address to start it booting. This doesn't have
29 Start address of zero-initialised work area for the decompressor.
34 This is the address where the decompressed kernel will be written,
43 Physical address to place the initial RAM disk. Only relevant if
48 Virtual address of the initial RAM disk. The following constraint
54 Physical address of the struct param_struct or tag list, giving the
62 Physical start address of the first bank of RAM.
65 Virtual start address of the first bank of RAM. During the kernel
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/Documentation/devicetree/bindings/i3c/
Di3c.yaml22 "#address-cells":
27 All I3C devices are supposed to support DAA (Dynamic Address Assignment),
35 this I3C device has a static I2C address and we want to assign it a
36 specific I3C dynamic address before the DAA takes place (so that other
37 devices on the bus can't take this dynamic address).
65 - "#address-cells"
72 I2C child, should be named: <device-type>@<i2c-address>
86 I2C address. 10 bit addressing is not supported. Devices with
87 10-bit address can't be properly passed through DEFSLVS
117 I3C child, should be named: <device-type>@<static-i2c-address>,<i3c-pid>
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/Documentation/arch/xtensa/
Dbooting.rst8 entry must have type BP_TAG_LAST. The address of the first list entry is
9 passed to the kernel in the register a2. The address type depends on MMU type:
12 address must be the physical address.
14 the address must be a valid address in the current mapping. The kernel will
16 - For configurations with MMUv2 the address must be a virtual address in the
18 - For configurations with MMUv3 and CONFIG_MMU=y the address may be either a
19 virtual or physical address. In either case it must be within the default
/Documentation/userspace-api/media/cec/
Dcec-ioc-adap-g-phys-addr.rst15 CEC_ADAP_G_PHYS_ADDR, CEC_ADAP_S_PHYS_ADDR - Get or set the physical address
35 Pointer to the CEC address.
40 To query the current physical address applications call
42 driver stores the physical address.
44 To set a new physical address applications store the physical address in
52 To clear an existing physical address use ``CEC_PHYS_ADDR_INVALID``.
55 If logical address types have been defined (see :ref:`ioctl CEC_ADAP_S_LOG_ADDRS <CEC_ADAP_S_LOG_AD…
60 A :ref:`CEC_EVENT_STATE_CHANGE <CEC-EVENT-STATE-CHANGE>` event is sent when the physical address
63 The physical address is a 16-bit number where each group of 4 bits
64 represent a digit of the physical address a.b.c.d where the most
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/Documentation/devicetree/bindings/powerpc/fsl/
Dmsi-pic.txt14 the address and the length of the shared message interrupt register set.
15 The second region should contain the address of aliased MSIIR or MSIIR1
33 - msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register
34 is used for MSI messaging. The address of MSIIR in PCI address space is
35 the MSI message address.
81 The Freescale hypervisor and msi-address-64
84 Freescale MSI driver calculates the address of MSIIR (in the MSI register
85 block) and sets that address as the MSI message address.
91 The ATMU is programmed with the guest physical address, and the PAMU
92 intercepts transactions and reroutes them to the true physical address.
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/Documentation/ABI/testing/
Dsysfs-bus-rpmsg19 processor. Channels have a local ("source") rpmsg address,
20 and remote ("destination") rpmsg address. When an entity
22 a unique rpmsg address (a 32 bits integer). This way when
23 inbound messages arrive to this address, the rpmsg core
26 This sysfs entry contains the src (local) rpmsg address
27 of this channel. If it contains 0xffffffff, then an address
37 processor. Channels have a local ("source") rpmsg address,
38 and remote ("destination") rpmsg address. When an entity
40 a unique rpmsg address (a 32 bits integer). This way when
41 inbound messages arrive to this address, the rpmsg core
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Ddebugfs-cxl6 (WO) When a Device Physical Address (DPA) is written to this
8 the device for the specified address. The DPA must be 64-byte
10 successful, the device returns poison when the address is
12 address to the device's Poison List and the error source is set
16 It is not an error to inject poison into an address that
28 (WO) When a Device Physical Address (DPA) is written to this
30 the device for the specified address. Clearing poison removes
31 the address from the device's Poison List and writes 0 (zero)
32 for 64 bytes starting at address. It is not an error to clear
33 poison from an address that does not have poison set. If the
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/Documentation/devicetree/bindings/i2c/
Di2c-atr.yaml7 title: Common i2c address translator properties
13 An I2C Address Translator (ATR) is a device with an I2C slave parent
16 with a modified slave address. The address used on the parent bus is
18 slave address of the child bus. Address translation is done by the
29 that address will be forwarded to the remote peripheral, with the address
30 translated to the remote peripheral's real address. This property is not
Di2c-pxa-pci-ce4100.txt11 number to its physical address and to use this to find the child nodes
15 ranges describes how the parent pci address space
17 address space (first group of 2) and the size of
19 the first cell of the local address is chosen to be
25 ranges allows the address mapping to be described
32 #address-cells = <2>;
43 * three is the bar number followed by the 64bit bar address
44 * followed by size of the mapping. The bar address
53 #address-cells = <1>;
66 #address-cells = <1>;
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/Documentation/i2c/
Di2c-address-translators.rst4 I2C Address Translators
13 An I2C Address Translator (ATR) is a device with an I2C slave parent
16 with a modified slave address. The address used on the parent bus is
18 slave address of the child bus. Address translation is done by the
22 - the address on the parent and child busses can be different
52 propagates them on bus B or bus C or none depending on the device address
68 - Slave X driver requests a transaction (on adapter B), slave address 0x10
70 messages with address 0x20, forwards to adapter A
71 - Physical I2C transaction on bus A, slave address 0x20
72 - ATR chip detects transaction on address 0x20, finds it in table,
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/Documentation/devicetree/bindings/pwm/
Dpwm-tipwmss.txt9 - reg: physical base address and size of the registers map.
10 - address-cells: Specify the number of u32 entries needed in child nodes.
14 - ranges: describes the address mapping of a memory-mapped bus. Should set to
15 physical address map of child's base address, physical address within
16 parent's address space and length of the address map. For am33xx,
27 #address-cells = <1>;
40 #address-cells = <1>;
53 #address-cells = <1>;
/Documentation/devicetree/bindings/pci/
Dralink,rt3883-pci.txt9 - reg: specifies the physical base address of the controller and
12 - #address-cells: specifies the number of cells needed to encode an
13 address. The value must be 1.
16 of an address. The value must be 1.
18 - ranges: specifies the translation between child address space and parent
19 address space
37 - #address-cells: specifies the number of cells needed to encode an
38 address. The value must be 0. As such, 'interrupt-map' nodes do not
39 have to specify a parent unit address.
52 - #address-cells: specifies the number of cells needed to encode an
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/Documentation/arch/arm64/
Dtagged-pointers.rst15 the virtual address ignored by the translation hardware. This frees up
23 an address tag of 0x00, unless the application enables the AArch64
24 Tagged Address ABI explicitly
25 (Documentation/arch/arm64/tagged-address-abi.rst).
38 Using non-zero address tags in any of these locations when the
39 userspace application did not enable the AArch64 Tagged Address ABI may
43 For these reasons, when the AArch64 Tagged Address ABI is disabled,
44 passing non-zero address tags to the kernel via system calls is
45 forbidden, and using a non-zero address tag for sp is strongly
49 address tags may suffer impaired or inaccurate debug and profiling
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/Documentation/mm/
Dactive_mm.rst30 - we have "real address spaces" and "anonymous address spaces". The
31 difference is that an anonymous address space doesn't care about the
33 anonymous address space we just leave the previous address space
36 The obvious use for a "anonymous address space" is any thread that
44 - "tsk->mm" points to the "real address space". For an anonymous process,
46 really doesn't _have_ a real address space at all.
48 - however, we obviously need to keep track of which address space we
50 which shows what the currently active address space is.
52 The rule is that for a process with a real address space (ie tsk->mm is
58 anonymous process gets scheduled away, the borrowed address space is
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/Documentation/devicetree/bindings/usb/
Docteon-usb.txt9 - reg: specifies the physical base address of the USBN block and
12 - #address-cells: specifies the number of cells needed to encode an
13 address. The value must be 2.
16 of an address. The value must be 2.
18 - ranges: specifies the translation between child address space and parent
19 address space.
40 - reg: specifies the physical base address of the USBC block and
51 #address-cells = <2>;
/Documentation/core-api/
Dcachetlb.rst19 if it can be proven that a user address space has never executed
21 for this address space on that cpu.
25 virtual-->physical address translations obtained from the software
43 This interface flushes an entire user address space from
45 any previous page table modifications for the address space
49 This interface is used to handle whole address space
57 address translations from the TLB. After running, this
59 modifications for the address space 'vma->vm_mm' in the range
78 address space is available via vma->vm_mm. Also, one may
84 page table modification for address space 'vma->vm_mm' for
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/Documentation/livepatch/
Dreliable-stacktrace.rst139 body the return address may be held in an arbitrary general purpose register.
162 Some trampolines temporarily modify the return address of a function in order
165 * An ftrace trampoline may modify the return address so that function graph
168 * A kprobes (or optprobes) trampoline may modify the return address so that
171 When this happens, the original return address will not be in its usual
173 unwinder can reliably determine the original return address and no unwind state
175 address in place of the trampoline and report this as reliable. Otherwise, an
178 Special care is required when identifying the original return address, as this
203 While the traced function runs its return address on the stack points to
204 the start of return_to_handler, and the original return address is stored in
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/Documentation/arch/parisc/
Ddebugging.rst14 rest of the kernel. To translate an absolute address to a virtual
15 address you can lookup in System.map, add __PAGE_OFFSET (0x10000000
25 address should match (one of the) processor HPAs (high addresses in
26 the I/O range); the System Responder address is the address real-mode
29 Typical values for the System Responder address are addresses larger
30 than __PAGE_OFFSET (0x10000000) which mean a virtual address didn't
31 get translated to a physical address before real-mode code tried to
/Documentation/misc-devices/
Dmax6875.rst55 The driver does not probe any address, so you explicitly instantiate the
63 The MAX6874/MAX6875 ignores address bit 0, so this driver attaches to multiple
64 addresses. For example, for address 0x50, it also reserves 0x51.
65 The even-address instance is called 'max6875', the odd one is 'dummy'.
73 Reads and writes are performed differently depending on the address range.
99 The command is the upper byte of the address: 0x80, 0x81, or 0x82.
100 The data word is the lower part of the address or'd with data << 8::
102 cmd = address >> 8;
103 val = (address & 0xff) | (data << 8);
107 To write 0x5a to address 0x8003::
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/Documentation/devicetree/bindings/bus/
Dsocionext,uniphier-system-bus.yaml11 the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
16 within each bank to the CPU-viewed address. The needed setup includes the
17 base address, the size of each bank. Optionally, some timing parameters can
30 "#address-cells":
33 The second cell is the address offset within the bank.
41 Provide address translation from the System Bus to the parent bus.
44 The address region(s) that can be assigned for the System Bus is
48 The address translation is arbitrary as long as the banks are assigned in
49 the supported address space with the required alignment and they do not
68 - "#address-cells"
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/Documentation/devicetree/bindings/net/
Dcavium-pip.txt14 - reg: The base address of the PIP's register bank.
16 - #address-cells: Must be <1>.
27 - #address-cells: Must be <1>.
50 #address-cells = <1>;
56 #address-cells = <1>;
63 local-mac-address = [ 00 0f b7 10 63 60 ];
69 local-mac-address = [ 00 0f b7 10 63 61 ];
75 local-mac-address = [ 00 0f b7 10 63 62 ];
81 local-mac-address = [ 00 0f b7 10 63 63 ];
88 #address-cells = <1>;
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/Documentation/PCI/
Dacpi-info.rst12 method for accessing PCI config space below it, the address space windows
33 reserving address space. The static tables are for things the OS needs to
45 describe all the address space they consume. This includes all the windows
58 spec defines Consumer/Producer only for the Extended Address Space
60 Address Space descriptors. Consequently, OSes have to assume all
63 Prior to the addition of Extended Address Space descriptors, the failure of
71 New architectures should be able to use "Consumer" Extended Address Space
74 ia64 kernels assume all address space descriptors, including "Consumer"
75 Extended Address Space ones, are windows, so it would not be safe to
80 anything else." So a PNP0C02 _CRS should claim any address space that is
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