Home
last modified time | relevance | path

Searched full:bch (Results 1 – 15 of 15) sorted by relevance

/Documentation/devicetree/bindings/mtd/
Dgpmi-nand.yaml37 - description: Address and length of bch block.
42 - const: bch
48 const: bch
128 - description: SoC gpmi bch clock
129 - description: SoC gpmi bch apb clock
130 - description: SoC per1 bch clock
149 - description: SoC gpmi bch apb clock
167 - description: SoC gpmi bch clock
168 - description: SoC gpmi bch apb clock
183 reg-names = "gpmi-nand", "bch";
[all …]
Dnvidia-tegra20-nand.txt28 Supported values with "hw" ECC mode are: "rs", "bch".
35 - BCH: 4, 8, 14, 16
60 nand-ecc-algo = "bch";
Dti,elm.yaml14 errors and the location of the error based on BCH algorithms
Dmxic-nand.txt34 nand-ecc-algo = "bch";
Dmediatek,nand-ecc-engine.yaml56 bch: ecc@1100e000 {
Dnand-chip.yaml49 enum: [hamming, bch, rs]
Dallwinner,sun4i-a10-nand.yaml59 const: bch
Dfsmc-nand.txt38 software-based BCH.
Dingenic,nand.yaml85 ecc-engine = <&bch>;
Drockchip,nand-controller.yaml104 If specified it indicates that a different BCH/ECC setting is
Dmediatek,mtk-nfc.yaml125 ecc-engine = <&bch>;
Dbrcm,brcmnand.yaml139 determines how the hardware BCH engine will lay
Datmel-nand.txt139 capable of BCH encoding and decoding, on devices where it is present.
/Documentation/devicetree/bindings/dma/
Dingenic,dma.yaml73 1, which can be configured to have special behaviour for NAND/BCH
/Documentation/devicetree/bindings/spi/
Dmediatek,spi-mtk-snfi.yaml112 nand-ecc-engine = <&bch>;