| /Documentation/networking/ |
| D | bridge.rst | 11 operation of bridges in computer networks. A bridge, in the context of this
14 model. The purpose of a bridge is to filter and forward frames between
17 Bridge kAPI
20 Here are some core structures of bridge code. Note that the kAPI is *unstable*,
23 .. kernel-doc:: net/bridge/br_private.h
26 Bridge uAPI
29 Modern Linux bridge uAPI is accessed via Netlink interface. You can find
30 below files where the bridge and bridge port netlink attributes are defined.
32 Bridge netlink attributes
36 :doc: Bridge enum definition
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| D | switchdev.rst | 155 together to form a LAG. Two or more ports (or LAGs) can be bridged to bridge
158 tools such as the bridge driver, the bonding/team drivers, and netlink-based
163 bond will see its upper master change. If that bond is moved into a bridge,
172 to the switchdev device by mirroring bridge FDB entries down to the device. An
177 - Static FDB entries installed on a bridge port
187 static bridge FDB entry::
189 bridge fdb add dev DEV ADDRESS [vlan VID] [self] static
196 implementation of the ``DEV`` device itself. If ``DEV`` is a bridge port, this
197 will bypass the bridge and therefore leave the software database out of sync
202 bridge fdb add dev DEV ADDRESS [vlan VID] master static
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| /Documentation/networking/device_drivers/ethernet/ti/ |
| D | cpsw_switchdev.rst | 34 to the same bridge, but without enabling "switch" mode, or to different
63 which, by default, equal CPSW Port numbers. As result, bridge has to be
66 ip link add name br0 type bridge
67 ip link set dev br0 type bridge vlan_filtering 0
68 echo 0 > /sys/class/net/br0/bridge/default_pvid
74 ip link add name br0 type bridge
75 ip link set dev br0 type bridge vlan_filtering 0
76 echo 100 > /sys/class/net/br0/bridge/default_pvid
77 ip link set dev br0 type bridge vlan_filtering 1
91 Port's netdev devices have to be in UP before joining to the bridge to avoid
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| D | am65_nuss_cpsw_switchdev.rst | 41 Port's netdev devices have to be in UP before joining to the bridge to avoid
42 overwriting of bridge configuration as CPSW switch driver completely reloads its
45 When the both interfaces joined the bridge - CPSW switch driver will enable
50 Bridge setup
58 ip link add name br0 type bridge
59 ip link set dev br0 type bridge ageing_time 1000
65 [*] bridge vlan add dev br0 vid 1 pvid untagged self
77 ip link set dev BRDEV type bridge stp_state 1/0
84 bridge vlan add dev br0 vid 1 pvid untagged self <---- add cpu port to VLAN 1
86 Note. This step is mandatory for bridge/default_pvid.
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| /Documentation/driver-api/fpga/ |
| D | fpga-bridge.rst | 1 FPGA Bridge
4 API to implement a new FPGA bridge
7 * struct fpga_bridge - The FPGA Bridge structure
8 * struct fpga_bridge_ops - Low level Bridge driver ops
9 * __fpga_bridge_register() - Create and register a bridge
10 * fpga_bridge_unregister() - Unregister a bridge
13 the module that registers the FPGA bridge as the owner.
15 .. kernel-doc:: include/linux/fpga/fpga-bridge.h
18 .. kernel-doc:: include/linux/fpga/fpga-bridge.h
21 .. kernel-doc:: drivers/fpga/fpga-bridge.c
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| /Documentation/devicetree/bindings/fpga/ |
| D | altr,freeze-bridge-controller.yaml | 4 $id: http://devicetree.org/schemas/fpga/altr,freeze-bridge-controller.yaml#
7 title: Altera Freeze Bridge Controller
10 The Altera Freeze Bridge Controller manages one or more freeze bridges.
12 changes from passing through the bridge. The controller can also
13 unfreeze/enable the bridges which allows traffic to pass through the bridge
20 - $ref: fpga-bridge.yaml#
24 const: altr,freeze-bridge-controller
37 fpga-bridge@100000450 {
38 compatible = "altr,freeze-bridge-controller";
40 bridge-enable = <0>;
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| D | fpga-bridge.yaml | 4 $id: http://devicetree.org/schemas/fpga/fpga-bridge.yaml#
7 title: FPGA Bridge
14 pattern: "^fpga-bridge(@.*|-([0-9]|[1-9][0-9]+))?$"
16 bridge-enable:
18 0 if driver should disable bridge at startup
19 1 if driver should enable bridge at startup
20 Default is to leave bridge in current state.
28 fpga-bridge {
29 bridge-enable = <0>;
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| D | altr,socfpga-hps2fpga-bridge.yaml | 4 $id: http://devicetree.org/schemas/fpga/altr,socfpga-hps2fpga-bridge.yaml#
7 title: Altera FPGA/HPS Bridge
13 - $ref: fpga-bridge.yaml#
18 - altr,socfpga-lwhps2fpga-bridge
19 - altr,socfpga-hps2fpga-bridge
20 - altr,socfpga-fpga2hps-bridge
43 fpga-bridge@ff400000 {
44 compatible = "altr,socfpga-lwhps2fpga-bridge";
46 bridge-enable = <0>;
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| D | altr,socfpga-fpga2sdram-bridge.yaml | 4 $id: http://devicetree.org/schemas/fpga/altr,socfpga-fpga2sdram-bridge.yaml#
7 title: Altera FPGA To SDRAM Bridge
13 - $ref: fpga-bridge.yaml#
17 const: altr,socfpga-fpga2sdram-bridge
29 fpga-bridge@ffc25080 {
30 compatible = "altr,socfpga-fpga2sdram-bridge";
32 bridge-enable = <0>;
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| D | xlnx,pr-decoupler.yaml | 13 - $ref: fpga-bridge.yaml#
18 which prevents signal changes from passing through the bridge. The controller
20 bridge normally.
24 bridge. The controller safely handles AXI4MM and AXI4-Lite interfaces on a
28 Please refer to fpga-region.txt and fpga-bridge.txt in this directory for
61 fpga-bridge@100000450 {
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| /Documentation/networking/dsa/ |
| D | configuration.rst | 21 *bridge*
22 Every switch port is part of one configurable Ethernet bridge
26 Ethernet bridge.
75 *bridge*
108 *bridge*
120 # create bridge
121 ip link add name br0 type bridge
123 # add ports to bridge
128 # configure the bridge
131 # bring up the bridge
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| D | b53.rst | 57 VLAN configuration in the bridge showcase.
61 The configuration can only be set up via VLAN tagging and bridge setup.
82 # create bridge
83 ip link add name br0 type bridge
86 ip link set dev br0 type bridge vlan_filtering 1
94 bridge vlan add dev lan1 vid 2 pvid untagged
95 bridge vlan del dev lan1 vid 1
96 bridge vlan add dev lan2 vid 3 pvid untagged
97 bridge vlan del dev lan2 vid 1
104 # bring up the bridge devices
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| D | dsa.rst | 18 Linux tools such as bridge, iproute2, ifconfig to work transparently whether
477 DSA directly utilizes SWITCHDEV when interfacing with the bridge layer, and
495 to the standard iproute2 user space programs (ip-link, bridge), like address
757 ``BR_STATE_BLOCKING`` if the port is a bridge member, or ``BR_STATE_FORWARDING`` if it
764 disabled while being a bridge member
776 For example, all ports that belong to a VLAN-unaware bridge (which is
778 database associated by the driver with that bridge (and not with other
780 VLAN-unaware bridge port should be able to find a VLAN-unaware FDB entry having
782 same bridge. At the same time, the FDB lookup process must be able to not find
784 a port which is a member of a different VLAN-unaware bridge (and is therefore
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | marvell,orion-intc.txt | 26 * Bridge interrupt controller
29 - compatible: shall be "marvell,orion-bridge-intc"
30 - reg: base address of bridge interrupt registers starting with CAUSE register
31 - interrupts: bridge interrupt of the main interrupt controller
36 - marvell,#interrupts: number of interrupts provided by bridge interrupt
41 compatible = "marvell,orion-bridge-intc";
46 /* Dove bridge provides 5 interrupts */
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | simple-bridge.yaml | 4 $id: http://devicetree.org/schemas/display/bridge/simple-bridge.yaml#
41 description: The bridge input
45 description: The bridge output
53 description: GPIO controlling bridge enable
56 description: Power supply for the bridge
66 bridge {
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| D | cdns,mhdp8546.yaml | 4 $id: http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#
7 title: Cadence MHDP8546 bridge
41 DP bridge clock, used by the IP to know how to translate a number of
67 First input port representing the DP bridge input.
72 Second input port representing the DP bridge input.
77 Third input port representing the DP bridge input.
82 Fourth input port representing the DP bridge input.
87 Output port representing the DP bridge output.
135 mhdp: dp-bridge@f0fb000000 {
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| /Documentation/PCI/ |
| D | acpi-info.rst | 11 host bridges, so the ACPI namespace must describe each host bridge, the
13 the host bridge forwards to PCI (using _CRS), and the routing of legacy
16 PCI devices, which are below the host bridge, generally do not need to be
46 they forward down to the PCI bus, as well as registers of the host bridge
47 itself that are not forwarded to PCI. The host bridge registers include
49 range below the bridge, window registers that describe the apertures, etc.
52 the device-specific details. The host bridge registers also include ECAM
53 space, since it is consumed by the host bridge.
55 ACPI defines a Consumer/Producer bit to distinguish the bridge registers
56 ("Consumer") from the bridge apertures ("Producer") [4, 5], but early
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| /Documentation/devicetree/bindings/ata/ |
| D | cortina,gemini-sata-bridge.yaml | 4 $id: http://devicetree.org/schemas/ata/cortina,gemini-sata-bridge.yaml#
7 title: Cortina Systems Gemini SATA Bridge
13 The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
19 const: cortina,gemini-sata-bridge
75 cortina,gemini-enable-sata-bridge:
77 description: Enables the PATA to SATA bridge inside the Gemnini SoC.
96 compatible = "cortina,gemini-sata-bridge";
106 cortina,gemini-enable-sata-bridge;
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| /Documentation/devicetree/bindings/pci/ |
| D | pci.txt | 11 Additionally to the properties specified in the above standards a host bridge
15 If present this property assigns a fixed PCI domain number to a host bridge,
20 number for each host bridge in the system must be unique.
32 root port to downstream device and host bridge drivers can do programming
36 PCI-PCI Bridge properties
40 tree, as children of the host bridge node. Even though those devices are
47 Identifies the PCI-PCI bridge. As defined in the IEEE Std 1275-1994
52 The bus number is defined by firmware, through the standard bridge
55 register of the bridge directly above this port. Otherwise, the bus
59 If firmware leaves the ARI Forwarding Enable bit set in the bridge
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| /Documentation/ABI/testing/ |
| D | sysfs-class-fpga-bridge | 1 What: /sys/class/fpga_bridge/<bridge>/name
5 Description: Name of low level FPGA bridge driver.
7 What: /sys/class/fpga_bridge/<bridge>/state
11 Description: Show bridge state as "enabled" or "disabled"
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| /Documentation/devicetree/bindings/soc/imx/ |
| D | fsl,imx8mm-disp-blk-ctrl.yaml | 36 - const: csi-bridge
47 - const: csi-bridge-axi
48 - const: csi-bridge-apb
49 - const: csi-bridge-core
78 power-domain-names = "bus", "csi-bridge", "lcdif",
90 clock-names = "csi-bridge-axi", "csi-bridge-apb", "csi-bridge-core",
|
| /Documentation/arch/s390/ |
| D | qeth.rst | 5 OSA and HiperSockets Bridge Port Support
12 a primary or a secondary Bridge Port. For more information, see
15 When run on an OSA or HiperSockets Bridge Capable Port hardware, and the state
16 of some configured Bridge Port device on the channel changes, a udev
21 indicates that the Bridge Port device changed
30 When run on HiperSockets Bridge Capable Port hardware with host address
39 deregistered on the Bridge Port HiperSockets channel, or address
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| /Documentation/devicetree/bindings/clock/ |
| D | armada3700-periph-clock.txt | 6 There are two different blocks associated to north bridge and south
7 bridge.
12 The following is a list of provided IDs for Armada 3700 North bridge clocks:
33 The following is a list of provided IDs for Armada 3700 South bridge clocks:
54 north bridge block, or
55 "marvell,armada-3700-periph-clock-sb" for the south bridge block
56 - reg : must be the register address of North/South Bridge Clock register
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| /Documentation/devicetree/bindings/sound/ |
| D | st,sta350.txt | 23 0: 2-channel (full-bridge) power, 2-channel data-out
24 1: 2 (half-bridge). 1 (full-bridge) on-board power
25 2: 2 Channel (Full-Bridge) Power, 1 Channel FFX
71 If present, power bridge correction for THD reduction near maximum
93 - st,bridge-immediate-off:
94 If present, the bridge will be switched off immediately after the
95 power-down-gpio goes low. Otherwise, the bridge will wait for 13
108 If present, the bridge power-down time will be divided by the provided
121 // (full-bridge) power,
126 st,max-power-correction; // enables power bridge
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| /Documentation/devicetree/bindings/mmc/ |
| D | socionext,uniphier-sd.yaml | 39 bridge: exist only for version 2.91
45 - const: bridge
51 - const: bridge
80 const: bridge
86 const: bridge
108 reset-names = "host", "bridge";
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