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| /Documentation/input/devices/ |
| D | alps.rst | 33 00-00-64 if no buttons are pressed. The bits 0-2 of the first byte will be 1s
52 one-byte device registers in a 16-bit address space. The command sequence
54 with 88-07 followed by a third byte. This third byte can be used to determine
76 sequences for the "Dolphin" touchpads as determined by the second byte
94 byte 0: 0 0 YSGN XSGN 1 M R L
95 byte 1: X7 X6 X5 X4 X3 X2 X1 X0
96 byte 2: Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
109 byte 0: 1 0 0 0 1 x9 x8 x7
110 byte 1: 0 x6 x5 x4 x3 x2 x1 x0
111 byte 2: 0 ? ? l r ? fin ges
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| D | elantech.rst | 20 4.2 Native relative mode 4 byte packet format
21 4.3 Native absolute mode 4 byte packet format
24 5.2 Native absolute mode 6 byte packet format
30 6.2 Native absolute mode 6 byte packet format
35 7.2 Native absolute mode 6 byte packet format
41 8.2 Native relative mode 6 byte packet format
188 A: 1 = absolute mode (needs 4 byte packets, see reg_11)
201 F: 1 = enable native 4 byte packet mode
235 Native relative mode 4 byte packet format
238 byte 0::
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| D | sentelic.rst | 28 BYTE |---------------|BYTE |---------------|BYTE|---------------|BYTE|---------------|
32 Byte 1: Bit7 => Y overflow
40 Byte 2: X Movement(9-bit 2's complement integers)
41 Byte 3: Y Movement(9-bit 2's complement integers)
42 Byte 4: Bit3~Bit0 => the scrolling wheel's movement since the last data report.
60 BYTE |---------------|BYTE |---------------|BYTE|---------------|BYTE|---------------|
64 Byte 1: Bit7 => Y overflow
72 Byte 2: X Movement(9-bit 2's complement integers)
73 Byte 3: Y Movement(9-bit 2's complement integers)
74 Byte 4: Bit0 => the Vertical scrolling movement downward.
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| /Documentation/scsi/ |
| D | arcmsr_spec.rst | 49 Currently 128 byte buffer is used:
53 Byte 4--127 Max 124 bytes of data
171 byte 0 0xaa <-- signature
172 byte 1 0x55 <-- signature
173 byte 2 year (04)
174 byte 3 month (1..12)
175 byte 4 date (1..31)
176 byte 5 hour (0..23)
177 byte 6 minute (0..59)
178 byte 7 second (0..59)
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| /Documentation/netlink/specs/ |
| D | nftables.yaml | 23 byte-order: big-endian
242 byte-order: big-endian
253 byte-order: big-endian
260 byte-order: big-endian
265 byte-order: big-endian
281 byte-order: big-endian
295 byte-order: big-endian
300 byte-order: big-endian
314 byte-order: big-endian
321 byte-order: big-endian
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| D | ovs_flow.yaml | 57 byte-order: big-endian
65 byte-order: big-endian
70 byte-order: big-endian
93 byte-order: big-endian
99 byte-order: big-endian
104 byte-order: big-endian
149 byte-order: big-endian
153 byte-order: big-endian
161 byte-order: big-endian
165 byte-order: big-endian
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| /Documentation/i2c/ |
| D | smbus-protocol.rst | 24 single data byte, the functions using SMBus protocol operation names execute
46 Comm (8 bits) Command byte, a data byte which often selects a register on
48 Data (8 bits) A plain data byte. DataLow and DataHigh represent the low and
49 high byte of a 16 bit word.
50 Count (8 bits) A data byte containing the length of a block operation.
67 SMBus Receive Byte
72 This reads a single byte from a device, without specifying a device
82 SMBus Send Byte
87 This operation is the reverse of Receive Byte: it sends a single byte
88 to a device. See Receive Byte for more information.
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| D | slave-interface.rst | 63 types described hereafter. 'val' holds an u8 value for the data byte to be
87 'val': backend returns first byte to be sent
93 should transmit the first byte.
97 'val': bus driver delivers received byte
99 'ret': 0 if the byte should be acked, some errno if the byte should be nacked
101 Another I2C master has sent a byte to us which needs to be set in 'val'. If 'ret'
102 is zero, the bus driver should ack this byte. If 'ret' is an errno, then the byte
107 'val': backend returns next byte to be sent
111 The bus driver requests the next byte to be sent to another I2C master in
112 'val'. Important: This does not mean that the previous byte has been acked, it
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| D | i2c-stub.rst | 9 types of SMBus commands: write quick, (r/w) byte, (r/w) byte data, (r/w)
21 A pointer register with auto-increment is implemented for all byte
22 operations. This allows for continuous byte reads like those supported by
52 value 0x1f0000 would only enable the quick, byte and byte data
62 If your target driver polls some byte or word waiting for it to change, the
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| /Documentation/userspace-api/media/v4l/ |
| D | pixfmt-packed-yuv.rst | 15 - In all the tables that follow, bit 7 is the most significant bit in a byte.
30 seen in a 16-bit word, which is then stored in memory in little endian byte
51 - :cspan:`7` Byte 0 in memory
53 - :cspan:`7` Byte 1
159 format stores a pixel with Cr\ :sub:`7-0` in the first byte, Cb\ :sub:`7-0` in
160 the second byte and Y'\ :sub:`7-0` in the third byte.
168 - Byte 0
169 - Byte 1
170 - Byte 2
171 - Byte 3
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| D | metafmt-generic.rst | 29 **Byte Order Of V4L2_META_FMT_GENERIC_8.**
30 Each cell is one byte. "M" denotes a byte of metadata.
56 Data Units, with one padding byte after every four bytes of metadata. This
71 **Byte Order Of V4L2_META_FMT_GENERIC_CSI2_10.**
72 Each cell is one byte. "M" denotes a byte of metadata and "x" a byte of padding.
100 Data Units, with one padding byte after every two bytes of metadata. This format
115 **Byte Order Of V4L2_META_FMT_GENERIC_CSI2_12.**
116 Each cell is one byte. "M" denotes a byte of metadata and "x" a byte of padding.
156 **Byte Order Of V4L2_META_FMT_GENERIC_CSI2_14.**
157 Each cell is one byte. "M" denotes a byte of metadata and "x" a byte of padding.
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| D | pixfmt-sdr-pcu16be.rst | 23 **Byte Order.**
24 Each cell is one byte.
31 - Byte B0
32 - Byte B1
33 - Byte B2
34 - Byte B3
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| D | pixfmt-sdr-pcu18be.rst | 23 **Byte Order.**
24 Each cell is one byte.
31 - Byte B0
32 - Byte B1
33 - Byte B2
34 - Byte B3
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| D | pixfmt-sdr-pcu20be.rst | 23 **Byte Order.**
24 Each cell is one byte.
31 - Byte B0
32 - Byte B1
33 - Byte B2
34 - Byte B3
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| /Documentation/driver-api/ |
| D | mtdnand.rst | 367 Hardware ECC generator providing 3 bytes ECC per 256 byte.
371 Hardware ECC generator providing 3 bytes ECC per 512 byte.
375 Hardware ECC generator providing 6 bytes ECC per 512 byte.
379 Hardware ECC generator providing 8 bytes ECC per 512 byte.
645 The eccpos array holds the byte offsets in the spare area where the
693 256 byte pagesize
699 0x00 ECC byte 0 Error correction code byte 0
700 0x01 ECC byte 1 Error correction code byte 1
701 0x02 ECC byte 2 Error correction code byte 2
704 0x05 Bad block marker If any bit in this byte is zero, then this
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| /Documentation/ABI/testing/ |
| D | debugfs-dell-wmi-ddv | 12 - fan type (single byte)
28 - thermal type (single byte)
29 - current temperature (single byte)
30 - min. temperature (single byte)
31 - max. temperature (single byte)
32 - unknown field (single byte)
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| /Documentation/networking/ |
| D | x25-iface.rst | 21 over the LAPB link. The first byte of the skbuff indicates the meaning of
28 First Byte = 0x00 (X25_IFACE_DATA)
34 First Byte = 0x01 (X25_IFACE_CONNECT)
39 First Byte = 0x02 (X25_IFACE_DISCONNECT)
44 First Byte = 0x03 (X25_IFACE_PARAMS)
52 First Byte = 0x00 (X25_IFACE_DATA)
57 First Byte = 0x01 (X25_IFACE_CONNECT)
62 First Byte = 0x02 (X25_IFACE_DISCONNECT)
67 First Byte = 0x03 (X25_IFACE_PARAMS)
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| /Documentation/staging/ |
| D | lzo.rst | 35 The first byte of the block follows a different encoding from other bytes, it
37 prior to that byte.
42 rate of at most 255 per extra byte (thus the compression ratio cannot exceed
45 length = byte & ((1 << #bits) - 1)
49 length += first-non-zero-byte
56 Certain encodings involve one extra byte, others involve two extra bytes
95 Byte sequences
98 First byte encoding::
105 17 : bitstream version. If the first byte is 17, and compressed
107 versioned bitstream), the next byte gives the bitstream version
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| /Documentation/devicetree/bindings/clock/ |
| D | qcom,mmcc.yaml | 86 - description: DSI phy instance 1 byte clock
88 - description: DSI phy instance 2 byte clock
118 - description: DSI phy instance 0 byte clock
146 - description: DSI phy instance 0 byte clock
148 - description: DSI phy instance 1 byte clock
185 - description: DSI phy instance 0 byte clock
187 - description: DSI phy instance 1 byte clock
236 - description: DSI phy instance 0 byte clock
238 - description: DSI phy instance 1 byte clock
266 - description: DSI phy instance 0 byte clock
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| /Documentation/hid/ |
| D | hid-alps.rst | 22 Byte Field Value Notes
74 Byte1 Command Byte
75 Byte2 Address - Byte 0 (LSB)
76 Byte3 Address - Byte 1
77 Byte4 Address - Byte 2
78 Byte5 Address - Byte 3 (MSB)
79 Byte6 Value Byte
83 Command Byte is read=0xD1/write=0xD2.
87 Value Byte is writing data when you send the write commands.
94 Byte1 Response Byte
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| D | hidraw.rst | 51 On a device which uses numbered reports, the first byte of the returned data
53 byte. For devices which do not use numbered reports, the report data
54 will begin at the first byte.
63 The first byte of the buffer passed to write() should be set to the report
64 number. If the device does not use numbered reports, the first byte should
65 be set to 0. The report data itself should begin at the second byte.
116 Set the first byte of the supplied buffer to the report number. For devices
117 which do not use numbered reports, set the first byte to 0. The report data
118 begins in the second byte. Make sure to set len accordingly, to one more
125 endpoint. The first byte of the supplied buffer should be set to the report
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| /Documentation/devicetree/bindings/mtd/ |
| D | fsmc-nand.txt | 11 defaults to 1 byte
15 byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits
18 byte 1 TAR : ALE to RE delay, 4 bits are valid. Same format as TCLR.
19 byte 2 THIZ : number of HCLK clock cycles during which the data bus is
23 byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
26 byte 4 TWAIT : number of HCLK clock cycles to assert the command to the
29 byte 5 TSET : number of HCLK clock cycles to assert the address before the
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| /Documentation/hwmon/ |
| D | abituguru-datasheet.rst | 117 Then for each byte of data you want to read wait for DATA to hold 0x01
119 DATA holds 0x01 read the byte from CMD.
136 Then for each byte of data you want to write wait for DATA to hold 0x00
138 once DATA holds 0x00 write the byte to CMD.
171 Byte 0:
172 This byte holds the alarm flags for sensor 0-7 of Sensor Bank1, with bit 0
175 Byte 1:
176 This byte holds the alarm flags for sensor 8-15 of Sensor Bank1, with bit 0
179 Byte 2:
180 This byte holds the alarm flags for sensor 0-5 of Sensor Bank2, with bit 0
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| /Documentation/w1/masters/ |
| D | w1-uart.rst | 21 combination of baud-rate and transmitted byte, which corresponds to a
25 the baud-rate 9600, i.e. 104.2 us per bit. The transmitted byte 0xf0 over
27 for 1-Wire to 521 us. A present 1-Wire device changes the received byte by
32 115200, i.e. 8.7 us per bit. The transmitted byte 0x80 is used for a
33 Write-0 operation (low time 69.6us) and the byte 0xff for Read-0, Read-1
38 is different from the requested one, the transmitted byte is adapted
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| /Documentation/userspace-api/media/cec/ |
| D | cec-pin-error-inj.rst | 47 # <op>[,<mode>] rx-add-byte add a spurious byte to the received CEC message
48 # <op>[,<mode>] rx-remove-byte remove the last byte from the received CEC message
59 # <op>[,<mode>] tx-early-eom set the EOM bit one byte too soon
61 # <op>[,<mode>] tx-remove-byte drop the last byte from the message
74 # 10 bits per 'byte': bits 0-7: data, bit 8: EOM, bit 9: ACK
157 Every byte of the message will be NACKed in case the transmitter
158 keeps transmitting after the first byte was NACKed.
169 ``<op>[,<mode>] rx-add-byte``
170 Add a spurious 0x55 byte to the received CEC message, provided
174 ``<op>[,<mode>] rx-remove-byte``
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