Searched full:cmu (Results 1 – 25 of 28) sorted by relevance
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| /Documentation/devicetree/bindings/clock/ |
| D | samsung,exynos5433-clock.yaml | 29 - samsung,exynos5433-cmu-top
31 - samsung,exynos5433-cmu-cpif
33 - samsung,exynos5433-cmu-mif
36 - samsung,exynos5433-cmu-peric
38 - samsung,exynos5433-cmu-peris
40 - samsung,exynos5433-cmu-fsys
41 - samsung,exynos5433-cmu-g2d
43 - samsung,exynos5433-cmu-disp
44 - samsung,exynos5433-cmu-aud
45 - samsung,exynos5433-cmu-bus0
[all …]
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| D | samsung,exynos850-clock.yaml | 17 Exynos850 clock controller is comprised of several CMU units, generating
18 clocks for different domains. Those CMU units are modeled as separate device
23 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
34 - samsung,exynos850-cmu-top
35 - samsung,exynos850-cmu-apm
36 - samsung,exynos850-cmu-aud
37 - samsung,exynos850-cmu-cmgp
38 - samsung,exynos850-cmu-core
39 - samsung,exynos850-cmu-cpucl0
40 - samsung,exynos850-cmu-cpucl1
[all …]
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| D | actions,owl-cmu.txt | 1 * Actions Semi Owl Clock Management Unit (CMU)
10 "actions,s900-cmu"
11 "actions,s700-cmu"
12 "actions,s500-cmu"
23 dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h or
24 actions,s500-cmu.h header and can be used in device tree sources.
31 Actions Semi S900 CMU also requires one more clock:
36 cmu: clock-controller@e0160000 {
37 compatible = "actions,s900-cmu";
51 clocks = <&cmu CLK_UART5>;
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| D | google,gs101-clock.yaml | 13 Google GS101 clock controller is comprised of several CMU units, generating
14 clocks for different domains. Those CMU units are modeled as separate device
19 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
30 - google,gs101-cmu-top
31 - google,gs101-cmu-apm
32 - google,gs101-cmu-misc
33 - google,gs101-cmu-hsi0
34 - google,gs101-cmu-hsi2
35 - google,gs101-cmu-peric0
36 - google,gs101-cmu-peric1
[all …]
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| D | samsung,exynosautov9-clock.yaml | 17 Exynos Auto v9 clock controller is comprised of several CMU units, generating
18 clocks for different domains. Those CMU units are modeled as separate device
23 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
35 - samsung,exynosautov9-cmu-top
36 - samsung,exynosautov9-cmu-busmc
37 - samsung,exynosautov9-cmu-core
38 - samsung,exynosautov9-cmu-dpum
39 - samsung,exynosautov9-cmu-fsys0
40 - samsung,exynosautov9-cmu-fsys1
41 - samsung,exynosautov9-cmu-fsys2
[all …]
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| D | samsung,exynosautov920-clock.yaml | 16 ExynosAuto v920 clock controller is comprised of several CMU units, generating
17 clocks for different domains. Those CMU units are modeled as separate device
22 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
34 - samsung,exynosautov920-cmu-top
35 - samsung,exynosautov920-cmu-peric0
36 - samsung,exynosautov920-cmu-peric1
37 - samsung,exynosautov920-cmu-misc
38 - samsung,exynosautov920-cmu-hsi0
39 - samsung,exynosautov920-cmu-hsi1
60 const: samsung,exynosautov920-cmu-top
[all …]
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| D | samsung,exynos7885-clock.yaml | 17 Exynos7885 clock controller is comprised of several CMU units, generating
18 clocks for different domains. Those CMU units are modeled as separate device
23 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
34 - samsung,exynos7885-cmu-top
35 - samsung,exynos7885-cmu-core
36 - samsung,exynos7885-cmu-fsys
37 - samsung,exynos7885-cmu-peri
58 const: samsung,exynos7885-cmu-top
74 const: samsung,exynos7885-cmu-core
96 const: samsung,exynos7885-cmu-fsys
[all …]
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| D | samsung,exynos-clock.yaml | 23 - samsung,exynos3250-cmu
24 - samsung,exynos3250-cmu-dmc
25 - samsung,exynos3250-cmu-isp
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| D | tesla,fsd-clock.yaml | 15 (CMU), which generates clocks for various internal SoC blocks.
24 - tesla,fsd-clock-cmu
51 const: tesla,fsd-clock-cmu
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| /Documentation/devicetree/bindings/net/ |
| D | actions,owl-emac.yaml | 72 #include <dt-bindings/clock/actions,s500-cmu.h>
80 clocks = <&cmu 59 /*CLK_ETHERNET*/>, <&cmu CLK_RMII_REF>;
82 resets = <&cmu RESET_ETHERNET>;
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| /Documentation/devicetree/bindings/serial/ |
| D | actions,owl-uart.yaml | 41 #include <dt-bindings/clock/actions,s500-cmu.h>
46 clocks = <&cmu CLK_UART0>;
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| /Documentation/devicetree/bindings/mmc/ |
| D | owl-mmc.yaml | 60 clocks = <&cmu 56>;
61 resets = <&cmu 23>;
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-owl.yaml | 52 #include <dt-bindings/clock/actions,s900-cmu.h>
58 clocks = <&cmu CLK_I2C0>;
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | samsung,exynos-adc.yaml | 162 clocks = <&cmu CLK_TSADC>,
163 <&cmu CLK_SCLK_TSADC>;
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| /Documentation/devicetree/bindings/arm/samsung/ |
| D | samsung-soc.yaml | 18 samsung,exynos5433-cmu-isp
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| /Documentation/devicetree/bindings/media/ |
| D | samsung,exynos4210-csis.yaml | 96 from CMU will be used, or the bus clock if it's not specified.
|
| /Documentation/ABI/testing/ |
| D | sysfs-firmware-qemu_fw_cfg | 3 Contact: Gabriel Somlo <somlo@cmu.edu>
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| /Documentation/arch/arm/sa1100/ |
| D | assabet.rst | 8 Also some notes from John G Dorsey <jd5q@andrew.cmu.edu>:
9 http://www.cs.cmu.edu/~wearable/software/assabet.html
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| /Documentation/devicetree/bindings/devfreq/event/ |
| D | samsung,exynos-ppmu.yaml | 104 clocks = <&cmu CLK_PPMURIGHT>;
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| /Documentation/devicetree/bindings/phy/ |
| D | samsung,usb3-drd-phy.yaml | 49 in the CMU.
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| /Documentation/devicetree/bindings/interconnect/ |
| D | samsung,exynos-bus.yaml | 271 clocks = <&cmu CLK_DIV_GDL>;
280 clocks = <&cmu CLK_DIV_GDR>;
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | actions,s700-pinctrl.txt | 148 clocks = <&cmu CLK_GPIO>;
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| D | actions,s500-pinctrl.yaml | 210 clocks = <&cmu 55>;
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| D | actions,s900-pinctrl.txt | 181 clocks = <&cmu CLK_GPIO>;
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| /Documentation/usb/ |
| D | CREDITS | 14 Bradley M Keryan <keryan@andrew.cmu.edu>
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