| /Documentation/devicetree/bindings/clock/ |
| D | mvebu-core-clock.txt | 1 * Core Clock bindings for Marvell MVEBU SoCs
3 Marvell MVEBU SoCs usually allow to determine core clock frequencies by
4 reading the Sample-At-Reset (SAR) register. The core clock consumer should
53 "marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
54 "marvell,armada-375-core-clock" - For Armada 375 SoC core clocks
55 "marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
56 "marvell,armada-390-core-clock" - For Armada 39x SoC core clocks
57 "marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
58 "marvell,mv98dx3236-core-clock" - For 98dx3236 family SoC core clocks
59 "marvell,dove-core-clock" - for Dove SoC core clocks
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| D | fsl,qoriq-clock-legacy.yaml | 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
22 - fsl,qoriq-core-pll-1.0
23 - fsl,qoriq-core-pll-2.0
24 - fsl,qoriq-core-mux-1.0
25 - fsl,qoriq-core-mux-2.0
74 - fsl,qoriq-core-pll-1.0
75 - fsl,qoriq-core-pll-2.0
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| /Documentation/arch/x86/ |
| D | topology.rst | 91 - On AMD, the Node ID or Core Complex ID containing the Last Level
97 A core consists of 1 or more threads. It does not matter whether the threads
100 AMDs nomenclature for a CMT core is "Compute Unit". The kernel always uses
101 "core".
108 AMDs nomenclature for CMT threads is "Compute Unit Core". The kernel always
122 The cpumask contains all online threads in the core to which a thread
135 The ID of the core to which a thread belongs. It is also printed in /proc/cpuinfo
150 1) Single Package, Single Core::
152 [package 0] -> [core 0] -> [thread 0] -> Linux CPU 0
154 2) Single Package, Dual Core
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| /Documentation/kbuild/ |
| D | Kconfig.recursion-issue-01 | 13 # * What values are possible for CORE?
15 # CORE_BELL_A_ADVANCED selects CORE, which means that it influences the values
16 # that are possible for CORE. So for example if CORE_BELL_A_ADVANCED is 'y',
17 # CORE must be 'y' too.
27 # CORE_BELL_A depends on CORE, so CORE influences CORE_BELL_A.
30 # what values are possible for CORE we ended up needing to address questions
31 # regarding possible values of CORE itself again. Answering the original
32 # question of what are the possible values of CORE would make the kconfig
38 # of the "select CORE" from CORE_BELL_A_ADVANCED as that is implicit already
39 # since CORE_BELL_A depends on CORE. Recursive dependency issues are not always
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| D | Kconfig.recursion-issue-02 | 11 # drivers if they share a common core requirement and use disjoint semantics to
14 # core requirement, and one uses "select" while the other uses "depends on" to
19 # core requirements are not carefully synced, as drivers evolve features
24 # describes a simple driver core layout of example features a kernel might
25 # have. Let's assume we have some CORE functionality, then the kernel has a
32 # with CORE, one uses "depends on" while the other uses "select". Another
38 # To fix this the "depends on CORE" must be changed to "select CORE", or the
39 # "select CORE" must be changed to "depends on CORE".
49 config CORE config
54 depends on CORE
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| /Documentation/devicetree/bindings/mips/loongson/ |
| D | devices.yaml | 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
20 - description: Classic Loongson64 Quad Core + LS7A
22 - const: loongson,loongson64c-4core-ls7a
24 - description: Classic Loongson64 Quad Core + RS780E
26 - const: loongson,loongson64c-4core-rs780e
28 - description: Classic Loongson64 Octa Core + RS780E
30 - const: loongson,loongson64c-8core-rs780e
32 - description: Generic Loongson64 Quad Core + LS7A
34 - const: loongson,loongson64g-4core-ls7a
36 - description: Virtual Loongson64 Quad Core + VirtIO
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| /Documentation/admin-guide/hw-vuln/ |
| D | core-scheduling.rst | 4 Core Scheduling
6 Core scheduling support allows userspace to define groups of tasks that can
7 share a core. These groups can be specified either for security usecases (one
9 workloads may benefit from running on the same core as they don't need the same
10 hardware resources of the shared core, or may prefer different cores if they
17 Threads of the same core. MDS and L1TF are examples of such attacks. The only
18 full mitigation of cross-HT attacks is to disable Hyper Threading (HT). Core
21 user-designated trusted group can share a core. This increase in core sharing
24 world workloads. In theory, core scheduling aims to perform at least as good as
27 core involves additional overhead - especially when the system is lightly
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| /Documentation/sound/kernel-api/ |
| D | alsa-driver-api.rst | 10 .. kernel-doc:: sound/core/init.c
14 .. kernel-doc:: sound/core/device.c
18 .. kernel-doc:: sound/core/sound.c
22 .. kernel-doc:: sound/core/memory.c
23 .. kernel-doc:: sound/core/memalloc.c
29 PCM Core
31 .. kernel-doc:: sound/core/pcm.c
32 .. kernel-doc:: sound/core/pcm_lib.c
33 .. kernel-doc:: sound/core/pcm_native.c
38 .. kernel-doc:: sound/core/pcm_misc.c
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| /Documentation/devicetree/bindings/regulator/ |
| D | nvidia,tegra-regulators-coupling.txt | 11 On Tegra20 SoC's there are 3 coupled regulators: CORE, RTC and CPU.
12 The CORE and RTC voltages shall be in a range of 170mV from each other
18 On Tegra30 SoC's there are 2 coupled regulators: CORE and CPU. The CORE
19 and CPU voltages shall be in a range of 300mV from each other and CORE
24 - nvidia,tegra-core-regulator: Boolean property that designates regulator
25 as the "Core domain" voltage regulator.
35 core_vdd_reg: core {
42 nvidia,tegra-core-regulator;
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| /Documentation/devicetree/bindings/input/ |
| D | ps2keyb-mouse-apbps2.txt | 1 Aeroflex Gaisler APBPS2 PS/2 Core, supporting Keyboard or Mouse.
3 The APBPS2 PS/2 core is available in the GRLIB VHDL IP core library.
5 Note: In the ordinary environment for the APBPS2 core, a LEON SPARC system,
15 For further information look in the documentation for the GLIB IP core library:
|
| /Documentation/misc-devices/ |
| D | xilinx_sdfec.rst | 15 For a full description of SD-FEC core features, see the `SD-FEC Product Guide (PG256) <https://www.…
38 The driver works with the SD-FEC core in two modes of operation:
50 - Activate the SD-FEC core
51 - Monitor the SD-FEC core for errors
52 - Retrieve the status and configuration of the SD-FEC core
61 - Activate the SD-FEC core
62 - Monitor the SD-FEC core for errors
63 - Retrieve the status and configuration of the SD-FEC core
72 …lus determines the current activate state of the core, for example, is the core bypassed or has th…
81 …ioctl: Provides the following ioctl commands that allows the application configure the SD-FEC core:
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| /Documentation/devicetree/bindings/usb/ |
| D | gr-udc.txt | 3 The GRUSBDC USB Device Controller core is available in the GRLIB VHDL
4 IP core library.
6 Note: In the ordinary environment for the core, a Leon SPARC system,
24 each OUT endpoint of the core. Fewer entries overrides the default sizes
30 each IN endpoint of the core. Fewer entries overrides the default sizes
33 For further information look in the documentation for the GLIB IP core library:
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| /Documentation/arch/arm/ |
| D | marvell.rst | 31 Core:
79 Core:
111 Core:
132 Core:
151 Core:
152 Sheeva ARMv7 compatible Dual-core or Quad-core PJ4B-MP
160 Core:
177 Core:
187 Core:
202 Core:
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| /Documentation/target/ |
| D | tcm_mod_builder.rst | 32 …target:/mnt/sdb/lio-core-2.6.git/Documentation/target# python tcm_mod_builder.py -p iSCSI -m tcm_n…
33 tcm_dir: /mnt/sdb/lio-core-2.6.git/Documentation/target/../../
36 /mnt/sdb/lio-core-2.6.git/Documentation/target/../../drivers/target/tcm_nab5000
39 /mnt/sdb/lio-core-2.6.git/Documentation/target/../../drivers/target/tcm_nab5000
41 /mnt/sdb/lio-core-2.6.git/Documentation/target/../../drivers/target/tcm_nab5000/tcm_nab5000_base.h
43 /mnt/sdb/lio-core-2.6.git/Documentation/target/../../include/target/target_core_fabric_ops.h
45 …/mnt/sdb/lio-core-2.6.git/Documentation/target/../../drivers/target/tcm_nab5000/tcm_nab5000_fabric…
47 …/mnt/sdb/lio-core-2.6.git/Documentation/target/../../drivers/target/tcm_nab5000/tcm_nab5000_fabric…
49 …/mnt/sdb/lio-core-2.6.git/Documentation/target/../../drivers/target/tcm_nab5000/tcm_nab5000_config…
51 /mnt/sdb/lio-core-2.6.git/Documentation/target/../../drivers/target/tcm_nab5000/Kbuild
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| /Documentation/hid/ |
| D | hid-transport.rst | 14 devices and register them with the HID bus. HID core then loads generic device
16 transport and device setup/management. HID core is responsible for
36 | HID Core |
52 Everything below "HID Core" is simplified in this graph as it is only of
61 They allocate HID device objects and register them with HID core. Transport
62 drivers are not required to register themselves with HID core. HID core is never
67 device. Once a device is registered with HID core, the callbacks provided via
68 this struct are used by HID core to communicate with the device.
71 HID core will operate a device as long as it is registered regardless of any
73 must unregister the device from HID core and HID core will stop using the
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| /Documentation/driver-api/ |
| D | infiniband.rst | 10 InfiniBand core interfaces
13 .. kernel-doc:: drivers/infiniband/core/iwpm_util.h
16 .. kernel-doc:: drivers/infiniband/core/cq.c
19 .. kernel-doc:: drivers/infiniband/core/cm.c
22 .. kernel-doc:: drivers/infiniband/core/rw.c
25 .. kernel-doc:: drivers/infiniband/core/device.c
28 .. kernel-doc:: drivers/infiniband/core/verbs.c
31 .. kernel-doc:: drivers/infiniband/core/packer.c
34 .. kernel-doc:: drivers/infiniband/core/sa_query.c
37 .. kernel-doc:: drivers/infiniband/core/ud_header.c
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| /Documentation/devicetree/bindings/arm/ |
| D | actions.yaml | 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
18 # The Actions Semi S500 is a quad-core ARM Cortex-A9 SoC.
28 - const: caninos,labrador-v2 # Labrador Core v2
36 # The Actions Semi S700 is a quad-core ARM Cortex-A53 SoC.
40 - const: caninos,labrador-v3 # Labrador Core v3
47 # The Actions Semi S900 is a quad-core ARM Cortex-A53 SoC.
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| D | arm,integrator.yaml | 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 They are ARMv4, ARMv5 and ARMv6-capable using different core tiles,
16 "core tiles" and referred to in the device tree as "core modules".
34 peripherals to make use of the core module. See ARM DUI 0159B.
45 - core-module@10000000
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| /Documentation/devicetree/bindings/mmc/ |
| D | snps,dwcmshc-sdhci.yaml | 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
50 - const: core
80 - description: core clock
85 - const: core
93 - description: core clock
101 - const: core
130 clock-names = "core", "bus", "axi", "block", "timer";
141 clock-names = "core", "bus";
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| /Documentation/hwmon/ |
| D | coretemp.rst | 5 * All Intel Core family
11 - 0xe (Pentium M DC), 0xf (Core 2 DC 65nm),
12 - 0x16 (Core 2 SC 65nm), 0x17 (Penryn 45nm),
30 inside Intel CPUs. This driver can read both the per-core and per-package
49 tempX_input Core temperature (in millidegrees Celsius).
54 tempX_label Contains string "Core X", where X is processor
70 22nm Core i5/i7 Processors
81 32nm Core i3/i5/i7 Processors
88 32nm Core i7 Extreme Processors
103 45nm Xeon Processors 5400 Quad-Core
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| /Documentation/devicetree/bindings/media/ |
| D | qcom,sdm845-venus.yaml | 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
31 - const: core
50 - const: core
76 - const: core
110 clock-names = "core", "iface", "bus";
120 clock-names = "core", "bus";
128 clock-names = "core", "bus";
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| /Documentation/devicetree/bindings/watchdog/ |
| D | starfive,jh7100-wdt.yaml | 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
42 - description: Core clock
47 - const: core
73 - description: Core reset
79 - description: Core reset
90 clock-names = "apb", "core";
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| /Documentation/features/sched/membarrier-sync-core/ |
| D | arch-support.txt | 2 # Feature name: membarrier-sync-core
4 # description: arch supports core serializing membarrier
17 # Given that xRET is not core serializing, we rely on FENCE.I for providing
18 # core serialization:
33 # instruction is core serializing, but not SYSEXIT.
39 # Given that neither SYSRET{L,Q}, nor SYSEXIT, are core serializing, we rely
40 # instead on write_cr3() performed by switch_mm() to provide core serialization
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| /Documentation/devicetree/bindings/phy/ |
| D | intel,combo-phy.yaml | 5 $schema: http://devicetree.org/meta-schemas/core.yaml#
30 - description: ComboPhy core registers
31 - description: PCIe app core control registers
35 - const: core
44 - const: core
99 reg-names = "core", "app";
104 reset-names = "phy", "core", "iphy0", "iphy1";
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| /Documentation/devicetree/bindings/display/msm/ |
| D | hdmi.yaml | 6 $schema: http://devicetree.org/meta-schemas/core.yaml#
55 core-vdda-supply:
62 core-vcc-supply:
128 - const: core
131 core-vcc-supplies: false
151 - const: core
171 - const: core
190 clock-names = "core",
197 core-vdda-supply = <&pm8921_hdmi_mvs>;
230 "core",
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