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/Documentation/devicetree/bindings/clock/
Drenesas,cpg-mssr.yaml4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#
13 On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse Generator)
18 - The CPG block generates various core clocks,
27 - renesas,r7s9210-cpg-mssr # RZ/A2
28 - renesas,r8a7742-cpg-mssr # RZ/G1H
29 - renesas,r8a7743-cpg-mssr # RZ/G1M
30 - renesas,r8a7744-cpg-mssr # RZ/G1N
31 - renesas,r8a7745-cpg-mssr # RZ/G1E
32 - renesas,r8a77470-cpg-mssr # RZ/G1C
33 - renesas,r8a774a1-cpg-mssr # RZ/G2M
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Drenesas,rzg2l-cpg.yaml4 $id: http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#
13 On Renesas RZ/{G2L,V2L}-alike SoC's, the CPG (Clock Pulse Generator) and Module
18 - The CPG block generates various core clocks,
27 - renesas,r9a07g043-cpg # RZ/G2UL{Type-1,Type-2} and RZ/Five
28 - renesas,r9a07g044-cpg # RZ/G2{L,LC}
29 - renesas,r9a07g054-cpg # RZ/V2L
30 - renesas,r9a08g045-cpg # RZ/G3S
31 - renesas,r9a09g011-cpg # RZ/V2M
41 Clock source to CPG can be either from external clock input (EXCLK) or
47 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
[all …]
Drenesas,cpg-clocks.yaml4 $id: http://devicetree.org/schemas/clock/renesas,cpg-clocks.yaml#
7 title: Renesas Clock Pulse Generator (CPG)
13 The Clock Pulse Generator (CPG) generates core clocks for the SoC. It
16 The CPG may also provide a Clock Domain for SoC devices, in combination with
17 the CPG Module Stop (MSTP) Clocks.
22 - const: renesas,r8a73a4-cpg-clocks # R-Mobile APE6
23 - const: renesas,r8a7740-cpg-clocks # R-Mobile A1
24 - const: renesas,r8a7778-cpg-clocks # R-Car M1
25 - const: renesas,r8a7779-cpg-clocks # R-Car H1
28 - renesas,r7s72100-cpg-clocks # RZ/A1H
[all …]
Drenesas,cpg-div6-clock.yaml4 $id: http://devicetree.org/schemas/clock/renesas,cpg-div6-clock.yaml#
7 title: Renesas CPG DIV6 Clock
13 The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
14 Generator (CPG). Their clock input is divided by a configurable factor from 1
24 - const: renesas,cpg-div6-clock
56 compatible = "renesas,r8a73a4-cpg-clocks";
67 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
Drenesas,rzv2h-cpg.yaml4 $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
7 title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG)
13 On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation
19 const: renesas,r9a09g057-cpg
38 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
40 <dt-bindings/clock/renesas,r9a09g057-cpg.h>,
73 compatible = "renesas,r9a09g057-cpg";
Drenesas,cpg-mstp-clocks.yaml4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#
7 title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks
13 The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are
30 - const: renesas,cpg-mstp-clocks
68 "renesas,cpg-mstp-clocks";
/Documentation/devicetree/bindings/usb/
Drenesas,rzv2m-usb3drd.yaml87 #include <dt-bindings/clock/r9a09g011-cpg.h>
97 clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_P>,
98 <&cpg CPG_MOD R9A09G011_USB_PCLK>;
100 power-domains = <&cpg>;
101 resets = <&cpg R9A09G011_USB_DRD_RESET>;
111 clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_H>,
112 <&cpg CPG_MOD R9A09G011_USB_PCLK>;
114 power-domains = <&cpg>;
115 resets = <&cpg R9A09G011_USB_ARESETN_H>;
123 clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_P>,
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/Documentation/devicetree/bindings/sound/
Drenesas,rsnd.yaml382 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
395 clocks = <&cpg CPG_MOD 1005>, /* SSI-ALL */
396 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, /* SSI9, SSI8 */
397 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, /* SSI7, SSI6 */
398 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, /* SSI5, SSI4 */
399 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, /* SSI3, SSI2 */
400 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, /* SSI1, SSI0 */
401 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, /* SRC9, SRC8 */
402 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, /* SRC7, SRC6 */
403 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, /* SRC5, SRC4 */
[all …]
/Documentation/devicetree/bindings/display/bridge/
Drenesas,dsi.yaml135 #include <dt-bindings/clock/r9a07g044-cpg.h>
150 clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
151 <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
152 <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
153 <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
154 <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
155 <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
157 resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,
158 <&cpg R9A07G044_MIPI_DSI_ARESET_N>,
159 <&cpg R9A07G044_MIPI_DSI_PRESET_N>;
[all …]
Drenesas,dsi-csi2-tx.yaml86 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
93 clocks = <&cpg CPG_MOD 415>,
94 <&cpg CPG_CORE R8A779A0_CLK_DSI>,
95 <&cpg CPG_CORE R8A779A0_CLK_CP>;
97 resets = <&cpg 415>;
Drenesas,lvds.yaml142 #include <dt-bindings/clock/renesas-cpg-mssr.h>
148 clocks = <&cpg CPG_MOD 727>;
150 resets = <&cpg 727>;
172 #include <dt-bindings/clock/renesas-cpg-mssr.h>
178 clocks = <&cpg CPG_MOD 727>,
183 resets = <&cpg 727>;
209 clocks = <&cpg CPG_MOD 727>,
214 resets = <&cpg 726>;
/Documentation/devicetree/bindings/spi/
Drenesas,rzv2m-csi.yaml67 #include <dt-bindings/clock/r9a09g011-cpg.h>
72 clocks = <&cpg CPG_MOD R9A09G011_CSI4_CLK>,
73 <&cpg CPG_MOD R9A09G011_CPERI_GRPH_PCLK>;
75 resets = <&cpg R9A09G011_CSI_GPH_PRESETN>;
76 power-domains = <&cpg>;
/Documentation/devicetree/bindings/media/
Drenesas,rzg2l-csi2.yaml108 #include <dt-bindings/clock/r9a07g044-cpg.h>
115 clocks = <&cpg CPG_MOD R9A07G044_CRU_SYSCLK>,
116 <&cpg CPG_MOD R9A07G044_CRU_VCLK>,
117 <&cpg CPG_MOD R9A07G044_CRU_PCLK>;
119 power-domains = <&cpg>;
120 resets = <&cpg R9A07G044_CRU_PRESETN>,
121 <&cpg R9A07G044_CRU_CMN_RSTB>;
Drenesas,vsp1.yaml101 #include <dt-bindings/clock/renesas-cpg-mssr.h>
109 clocks = <&cpg CPG_MOD 131>;
111 resets = <&cpg 131>;
116 #include <dt-bindings/clock/renesas-cpg-mssr.h>
124 clocks = <&cpg CPG_MOD 624>;
126 resets = <&cpg 624>;
Drenesas,rzg2l-cru.yaml137 #include <dt-bindings/clock/r9a07g044-cpg.h>
147 clocks = <&cpg CPG_MOD R9A07G044_CRU_VCLK>,
148 <&cpg CPG_MOD R9A07G044_CRU_PCLK>,
149 <&cpg CPG_MOD R9A07G044_CRU_ACLK>;
151 power-domains = <&cpg>;
152 resets = <&cpg R9A07G044_CRU_PRESETN>,
153 <&cpg R9A07G044_CRU_ARESETN>;
/Documentation/devicetree/bindings/iio/adc/
Drenesas,rzg2l-adc.yaml113 #include <dt-bindings/clock/r9a07g044-cpg.h>
120 clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
121 <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
123 power-domains = <&cpg>;
124 resets = <&cpg R9A07G044_ADC_PRESETN>,
125 <&cpg R9A07G044_ADC_ADRST_N>;
/Documentation/devicetree/bindings/display/
Drenesas,rzg2l-du.yaml120 #include <dt-bindings/clock/r9a07g044-cpg.h>
127 clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
128 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
129 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
131 resets = <&cpg R9A07G044_LCDC_RESET_N>;
132 power-domains = <&cpg>;
/Documentation/devicetree/bindings/dma/
Drenesas,rz-dmac.yaml109 #include <dt-bindings/clock/r9a07g044-cpg.h>
138 clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
139 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
141 power-domains = <&cpg>;
142 resets = <&cpg R9A07G044_DMAC_ARESETN>,
143 <&cpg R9A07G044_DMAC_RST_ASYNC>;
/Documentation/devicetree/bindings/reset/
Drenesas,rzg2l-usbphy-ctrl.yaml64 #include <dt-bindings/clock/r9a07g044-cpg.h>
70 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
71 resets = <&cpg R9A07G044_USB_PRESETN>;
72 power-domains = <&cpg>;
/Documentation/devicetree/bindings/thermal/
Drzg2l-thermal.yaml53 #include <dt-bindings/clock/r9a07g044-cpg.h>
59 clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>;
60 resets = <&cpg R9A07G044_TSU_PRESETN>;
61 power-domains = <&cpg>;
Drcar-gen3-thermal.yaml104 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
116 clocks = <&cpg CPG_MOD 522>;
118 resets = <&cpg 522>;
138 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
149 clocks = <&cpg CPG_MOD 919>;
151 resets = <&cpg 919>;
/Documentation/devicetree/bindings/i2c/
Drenesas,rzv2m.yaml65 #include <dt-bindings/clock/r9a09g011-cpg.h>
74 clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK0>;
75 resets = <&cpg R9A09G011_IIC_GPA_PRESETN>;
76 power-domains = <&cpg>;
/Documentation/devicetree/bindings/phy/
Drenesas,r8a779f0-ether-serdes.yaml44 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
50 clocks = <&cpg CPG_MOD 1506>;
52 resets = <&cpg 1506>;
Drenesas,rcar-gen3-pcie-phy.yaml43 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
50 clocks = <&cpg CPG_MOD 319>;
52 resets = <&cpg 319>;
/Documentation/devicetree/bindings/serial/
Drenesas,sci.yaml90 #include <dt-bindings/clock/r9a07g044-cpg.h>
105 clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;
107 power-domains = <&cpg>;
108 resets = <&cpg R9A07G044_SCI0_RST>;

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