Searched full:cpu1 (Results 1 – 25 of 43) sorted by relevance
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| /Documentation/devicetree/bindings/arm/altera/ |
| D | socfpga-system.txt | 6 - cpu1-start-addr : CPU1 start address in hex.
12 cpu1-start-addr = <0xffd080c4>;
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| /Documentation/translations/zh_CN/scheduler/ |
| D | sched-capacity.rst | 62 - work_per_hz(CPU1) = W/2
68 - capacity(CPU1) = C/2
79 CPU1 work ^
94 - max_freq(CPU1) = 2/3 * F
99 - capacity(CPU1) = C/3
108 workload on CPU1
109 CPU1 work ^
175 - capacity(CPU1) = C/3
184 CPU1 work ^
337 capacity(CPU1) = C / 3
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| D | sched-energy.rst | 152 CPU0 CPU1 CPU2 CPU3
168 * CPU1: 300 / 341 * 150 = 131
177 CPU0 CPU1 CPU2 CPU3
186 * CPU1: 100 / 341 * 150 = 43
195 CPU0 CPU1 CPU2 CPU3
203 * CPU1: 100 / 512 * 300 = 58
212 CPU0 CPU1 CPU2 CPU3
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| /Documentation/scheduler/ |
| D | sched-capacity.rst | 62 - work_per_hz(CPU1) = W/2
68 - capacity(CPU1) = C/2
70 To draw the parallel with Arm big.LITTLE, CPU0 would be a big while CPU1 would
81 CPU1 work ^
87 work W in T units of time. On the other hand, CPU1 has half the capacity of
97 - max_freq(CPU1) = 2/3 * F
102 - capacity(CPU1) = C/3
112 workload on CPU1
113 CPU1 work ^
191 - capacity(CPU1) = C/3
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| D | sched-energy.rst | 152 composed of two CPUs each. CPU0 and CPU1 are little CPUs; CPU2 and CPU3
179 CPU0 CPU1 CPU2 CPU3
186 CPU1 and CPU3. Then it will estimate the energy of the system if P was
192 **Case 1. P is migrated to CPU1**::
198 * CPU1: 300 / 341 * 150 = 131
207 CPU0 CPU1 CPU2 CPU3
216 * CPU1: 100 / 341 * 150 = 43
225 CPU0 CPU1 CPU2 CPU3
234 * CPU1: 100 / 512 * 300 = 58
243 CPU0 CPU1 CPU2 CPU3
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| /Documentation/translations/zh_CN/core-api/irq/ |
| D | irq-affinity.rst | 46 CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7
64 CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7
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| /Documentation/core-api/irq/ |
| D | irq-affinity.rst | 38 CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7
57 CPU0 CPU1 CPU2 CPU3 CPU4 CPU5 CPU6 CPU7
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| /Documentation/devicetree/bindings/cpu/ |
| D | cpu-topology.txt | 199 cpu = <&CPU1>;
284 CPU1: cpu@1 {
417 cpu = <&CPU1>;
449 CPU1: cpu@1 {
508 cpu = <&CPU1>;
523 CPU1: cpu@1 {
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| /Documentation/translations/zh_CN/infiniband/ |
| D | core_locking.rst | 86 CPU1 CPU2
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| /Documentation/dev-tools/ |
| D | gpio-sloppy-logic-analyzer.rst | 68 following settings are used: The isolated CPU shall be CPU1 because it is a big
69 core in a big.LITTLE setup. Because CPU1 is the default, we don't need a
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| /Documentation/devicetree/bindings/power/ |
| D | renesas,apmu.yaml | 56 cpus = <&cpu0>, <&cpu1>;
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| /Documentation/devicetree/bindings/arm/ |
| D | arm,cci-400.yaml | 135 * {CPU0, CPU1};
152 CPU1: cpu@1 {
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| D | psci.yaml | 203 CPU1: cpu@1 {
253 CPU_PD1: power-domain-cpu1 {
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| D | arm,coresight-etm.yaml | 148 cpu = <&cpu1>;
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| /Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-mediatek.txt | 198 cpu1: cpu@1 {
238 &cpu1 {
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| D | qcom-cpufreq-nvmem.yaml | 134 CPU1: cpu@101 {
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| D | cpufreq-qcom-hw.yaml | 242 CPU1: cpu@100 {
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| /Documentation/devicetree/bindings/cache/ |
| D | socionext,uniphier-system-cache.yaml | 31 The specified interrupts correspond to CPU0, CPU1, ... in this order.
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| /Documentation/arch/powerpc/ |
| D | vcpudispatch_stats.rst | 51 cpu1 2515 1274 1229 12 0 2509 6 0
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| /Documentation/devicetree/bindings/opp/ |
| D | opp-v2-kryo-cpu.yaml | 135 CPU1: cpu@1 {
192 cpu = <&CPU1>;
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| /Documentation/infiniband/ |
| D | core_locking.rst | 82 CPU1 CPU2
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| /Documentation/ |
| D | atomic_t.txt | 110 In this case we would expect the atomic_set() from CPU1 to either happen
121 CPU0 CPU1
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| /Documentation/devicetree/bindings/thermal/ |
| D | thermal-zones.yaml | 308 cooling-device = <&CPU0 3 3>, <&CPU1 3 3>,
315 cooling-device = <&CPU0 5 5>, <&CPU1 5 5>,
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| /Documentation/userspace-api/ |
| D | perf_ring_buffer.rst | 162 CPU1 |xxxxx|
227 CPU1 | |xxxxx| |
273 running on CPU1 and CPU3, since the ring buffer is absent for them, any
293 CPU1 |xxxxx|
349 CPU1 |xxxxx|
671 CPU1 |xxxxx|
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| /Documentation/devicetree/bindings/net/ |
| D | marvell,pp2.yaml | 93 "tx-cpu1", "tx-cpu2", "tx-cpu3" and "rx-shared" are supported
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