Searched full:cpuid (Results 1 – 25 of 44) sorted by relevance
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| /Documentation/virt/kvm/x86/ |
| D | errata.rst | 23 Unlike most other CPUID feature bits, CPUID[EAX=7,ECX=0]:EBX[6]
24 (FDP_EXCPTN_ONLY) and CPUID[EAX=7,ECX=0]:EBX]13] (ZERO_FCS_FDS) are
27 Clearing these bits in CPUID has no effect on the operation of the guest;
31 **Workaround:** It is recommended to always set these bits in guest CPUID.
33 to be present likely predates these CPUID feature bits, and therefore
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| D | cpuid.rst | 4 KVM CPUID bits
10 cpuid. This is not always guaranteed to work, since userspace can
11 mask-out some, or even all KVM-related cpuid features before launching
14 KVM cpuid functions are:
26 The value in eax corresponds to the maximum cpuid function present in this leaf,
30 This function queries the presence of KVM cpuid leafs.
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| D | msr.rst | 56 Availability of this MSR must be checked via bit 3 in 0x4000001 cpuid
128 of specific flags has to be checked in 0x40000001 cpuid leaf.
133 | flag bit | cpuid bit | meaning |
144 Availability of this MSR must be checked via bit 3 in 0x4000001 cpuid
157 Availability of this MSR must be checked via bit 0 in 0x4000001 cpuid
169 Availability of this MSR must be checked via bit 0 in 0x4000001 cpuid
174 if (!kvm_para_available()) /* refer to cpuid.txt */
214 present in CPUID. Bit 3 enables interrupt based delivery of 'page ready'
216 CPUID.
246 available if KVM_FEATURE_ASYNC_PF_INT is present in CPUID.
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| D | index.rst | 11 cpuid
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| D | hypercalls.rst | 70 :Purpose: Expose hypercall availability to the guest. On x86 platforms, cpuid
190 before advertising KVM_FEATURE_HC_MAP_GPA_RANGE in the guest CPUID. In
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| /Documentation/arch/x86/ |
| D | cpuinfo.rst | 19 CPUID to find out what the target machine supports and what not.
23 said CPU supports CPUID faulting - userspace can simply probe for the
32 kernel has *enabled* and *supports*. As in: the CPUID feature flag is
64 tools/arch/x86/kcpuid and cpuid(1).
73 unlikely. KVM can synthesize the CPUID bit and the KVM guest can simply
74 query CPUID and figure out what the hypervisor supports and what not. As
82 a: Feature flags can be derived from the contents of CPUID leaves.
84 These feature definitions are organized mirroring the layout of CPUID
92 b: Flags can be from scattered CPUID-based features.
94 Hardware features enumerated in sparsely populated CPUID leaves get
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| D | tsx_async_abort.rst | 27 controls the enumeration of the TSX feature bits (RTM and HLE) in CPUID.
44 advertised in CPUID.
47 advertised in CPUID. That is mainly for virtualization
49 hypervisor does not expose MD_CLEAR in CPUID. It's a best
55 status of RTM and MD_CLEAR CPUID bits.
116 (i.e. it will make CPUID(EAX=7).EBX{bit4} and
117 CPUID(EAX=7).EBX{bit11} read as 0).
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| D | mds.rst | 106 MD_CLEAR CPUID bit to guests, the kernel issues the VERW instruction in the
123 advertised in CPUID.
126 advertised in CPUID. That is mainly for virtualization
128 hypervisor does not expose MD_CLEAR in CPUID. It's a best
134 the availability of the MD_CLEAR CPUID bit.
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| D | amd-memory-encryption.rst | 42 Support for SME and SEV can be determined through the CPUID instruction. The
43 CPUID function 0x8000001f reports information related to SME::
72 CPUID information above) will not conflict with the address space resource
79 The CPU supports SME (determined through CPUID instruction).
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| D | xstate.rst | 5 enumerated via CPUID. Applications consult CPUID and use XGETBV to
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| D | tdx.rst | 226 - CPUID*
260 CPUID Behavior
263 For some CPUID leaves and sub-leaves, the virtualized bit fields of CPUID
276 A #VE is generated for CPUID leaves and sub-leaves that the TDX module does
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| /Documentation/virt/acrn/ |
| D | cpuid.rst | 4 ACRN CPUID bits
8 CPUID.
10 ACRN cpuid functions are:
22 "ACRNACRNACRN". The value in eax corresponds to the maximum cpuid function
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| D | index.rst | 12 cpuid
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| /Documentation/virt/coco/ |
| D | sev-guest.rst | 198 3. SEV-SNP CPUID Enforcement
201 SEV-SNP guests can access a special page that contains a table of CPUID values
203 command. It provides the following assurances regarding the validity of CPUID
213 a non-CPUID encrypted page will change the measurement provided by the
215 - The CPUID page contents are *not* measured, but attempts to modify the
216 expected contents of a CPUID page as part of guest initialization will be
217 gated by the PSP CPUID enforcement policy checks performed on the page
219 implements their own checks of the CPUID values.
222 has taken care to make use of the SEV-SNP CPUID throughout all stages of boot.
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| /Documentation/hwmon/ |
| D | fam15h_power.rst | 64 indicated by CPUID Fn8000_0007_EDX[12].
93 i. Determine the ratio of Tsample to Tref by executing CPUID Fn8000_0007.
95 N = value of CPUID Fn8000_0007_ECX[CpuPwrSampleTimeRatio[15:0]].
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| /Documentation/virt/kvm/loongarch/ |
| D | hypercalls.rst | 79 - a3: The lowest physical CPUID in the bitmap
85 Bit 0 of a1 corresponds to the physical CPUID in the third input register (a3)
86 and bit 1 corresponds to the physical CPUID in a3+1, and so on.
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| /Documentation/translations/zh_CN/virt/acrn/ |
| D | index.rst | 25 cpuid
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| D | cpuid.rst | 4 :Original: Documentation/virt/acrn/cpuid.rst
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| /Documentation/arch/arm/ |
| D | marvell.rst | 478 CPUID 0x69052xxx
481 CPUID 0x69054xxx
484 CPUID 0x69056xxx or 0x69056xxx
487 CPUID 0x5615331x or 0x41xx926x
490 CPUID 0x5605531x or 0x41xx926x
493 CPUID 0x5615571x
496 CPUID 0x5625131x
499 CPUID 0x561584xx
502 CPUID 0x560f581x
505 CPUID 0x561f581x
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| /Documentation/virt/hyperv/ |
| D | coco.rst | 116 * CPUID flags. Both AMD SEV-SNP and Intel TDX provide a CPUID flag in the
118 support. While these CPUID flags are visible in fully-enlightened CoCo VMs,
124 to selectively enable aspects of CoCo VM functionality even when the CPUID
126 tests the CPUID SEV-SNP flag. But not having the flag in Hyper-V paravisor
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| /Documentation/driver-api/thermal/ |
| D | x86_pkg_temperature_thermal.rst | 9 (Verify using: CPUID.06H:EAX[bit 6] =1)
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| /Documentation/admin-guide/hw-vuln/ |
| D | tsx_async_abort.rst | 105 based mitigation mechanism is not advertised via CPUID, the kernel
111 expose the CPUID to the guest. If the host has updated microcode the
176 and HLE) in CPUID.
225 combinations of CPUID bit MD_CLEAR and IA32_ARCH_CAPABILITIES MSR bits MDS_NO
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| D | reg-file-data-sampling.rst | 36 CPUID.HYBRID. This information could be used to distinguish between the
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| D | mds.rst | 109 based mitigation mechanism is not advertised via CPUID, the kernel
115 expose the CPUID to the guest. If the host has updated microcode the
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| /Documentation/virt/kvm/devices/ |
| D | vm.rst | 66 __u64 cpuid; # CPUID of host
85 __u64 cpuid; # CPUID currently (to be) used by this vcpu
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