| /Documentation/devicetree/bindings/memory-controllers/ |
| D | ti-aemif.txt | 34 - CS-specific partition/range. If continuous, must be 38 - control partition which is common for all CS 56 Child chip-select (cs) nodes contain the memory devices nodes connected to 60 Required child cs node properties: 73 - ti,cs-chipselect: number of chipselect. Indicates on the aemif driver 79 Optional child cs node properties: 81 - ti,cs-bus-width: width of the asynchronous device's data bus 84 - ti,cs-select-strobe-mode: enable/disable select strobe mode 89 - ti,cs-extended-wait-mode: enable/disable extended wait mode 95 - ti,cs-min-turnaround-ns: minimum turn around time, ns [all …]
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| D | st,stm32-fmc2-ebi-props.yaml | 14 st,fmc2-ebi-cs-transaction-type: 33 st,fmc2-ebi-cs-cclk-enable: 40 st,fmc2-ebi-cs-mux-enable: 46 st,fmc2-ebi-cs-buswidth: 52 st,fmc2-ebi-cs-waitpol-high: 57 st,fmc2-ebi-cs-waitcfg-enable: 64 st,fmc2-ebi-cs-wait-enable: 70 st,fmc2-ebi-cs-asyncwait-enable: 76 st,fmc2-ebi-cs-cpsize: 84 st,fmc2-ebi-cs-byte-lane-setup-ns: [all …]
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| D | st,stm32-fmc2-ebi.yaml | 86 ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ 87 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ 88 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ 89 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ 97 st,fmc2-ebi-cs-transaction-type = <1>; 98 st,fmc2-ebi-cs-address-setup-ns = <60>; 99 st,fmc2-ebi-cs-data-setup-ns = <30>; 100 st,fmc2-ebi-cs-bus-turnaround-ns = <5>;
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| D | arm,pl172.txt | 28 Child chip-select (cs) nodes contain the memory devices nodes connected to 31 Required child cs node properties: 44 - mpmc,cs: Chip select number. Indicates to the pl0172 driver 50 Optional child cs node config properties: 54 - mpmc,cs-active-high: Set chip select polarity to active high. 65 Optional child cs node timing properties: 107 mpmc,cs = <0>;
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| D | ti,gpmc-child.yaml | 29 gpmc,cs-on-ns: 33 gpmc,cs-rd-off-ns: 37 gpmc,cs-wr-off-ns: 132 gpmc,cs-extra-delay: 133 description: CS signal is delayed by half GPMC clock 139 to a different CS 145 to the same CS
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| /Documentation/devicetree/bindings/gpio/ |
| D | spear_spics.txt | 1 === ST Microelectronics SPEAr SPI CS Driver === 21 * st-spics,cs-value-bit: bit offset to drive chipselect low or high 22 * st-spics,cs-enable-mask: chip select number bit mask 23 * st-spics,cs-enable-shift: chip select number program offset 36 st-spics,cs-value-bit = <11>; 37 st-spics,cs-enable-mask = <3>; 38 st-spics,cs-enable-shift = <8>; 45 num-cs = <3>; 46 cs-gpios = <&gpio1 7 0>, <&spics 0>,
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-controller.yaml | 28 cs-gpios: 32 increased automatically with max(cs-gpios, hardware chip selects). 34 So if, for example, the controller has 4 CS lines, and the 35 cs-gpios looks like this 36 cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>; 49 cs-gpio with the optional spi-cs-high flag for SPI slaves. 51 Each table entry defines how the CS pin is to be physically 54 device node | cs-gpio | CS pin state active | Note 56 spi-cs-high | - | H | 58 spi-cs-high | ACTIVE_HIGH | H | [all …]
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| D | brcm,bcm2835-aux-spi.txt | 15 - cs-gpios: the cs-gpios (native cs is NOT supported) 27 cs-gpios = <&gpio 18>, <&gpio 17>, <&gpio 16>; 37 cs-gpios = <&gpio 43>, <&gpio 44>, <&gpio 45>;
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| D | spi-davinci.txt | 18 - num-cs: Number of chip selects. This includes internal as well as 39 - cs-gpios: gpio chip selects 40 For example to have 3 internal CS and 2 GPIO CS, user could define 41 cs-gpios = <0>, <0>, <0>, <&gpio1 30 0>, <&gpio1 31 0>; 42 where first three are internal CS and last two are GPIO CS. 76 num-cs = <4>;
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| D | spi-lantiq-ssc.txt | 19 - num-cs: see spi-bus.txt, set to 8 if unset 20 - base-cs: the number of the first chip select, set to 1 if unset. 33 num-cs = <6>; 34 base-cs = <1>;
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| D | spi-peripheral-props.yaml | 32 spi-cs-high: 47 spi-cs-setup-delay-ns: 49 Delay in nanoseconds to be introduced by the controller after CS is 52 spi-cs-hold-delay-ns: 54 Delay in nanoseconds to be introduced by the controller before CS is 57 spi-cs-inactive-delay-ns: 59 Delay in nanoseconds to be introduced by the controller after CS is
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| D | spi-cadence.yaml | 35 num-cs: 45 is-decoded-cs: 82 num-cs = <4>; 83 is-decoded-cs = <0>;
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| D | samsung,spi.yaml | 52 no-cs-readback: 54 The CS line is disconnected, therefore the device should not operate 55 based on CS signalling. 58 num-cs: 145 num-cs = <1>; 147 cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
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| D | microchip,mpfs-spi.yaml | 58 num-cs: 68 - cs-gpios 71 num-cs:
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| D | spi-mux.yaml | 23 | +--+++-+ | CS-X +------+\ +--+--+ +--+--+ +--+--+ +--+--+ 24 | | SPI +-|-------+ Mux |\\ CS-0 | | | | 25 | +------+ | +--+---+\\\-------/ CS-1 | | | 26 | | | \\\----------------/ CS-2 | | 27 | +------+ | | \\-------------------------/ CS-3 |
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| D | spi-fsl-lpspi.yaml | 57 spi common code does not support use of CS signals discontinuously. 62 num-cs: 96 num-cs = <2>;
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| D | fsl,dspi-peripheral-props.yaml | 16 fsl,spi-cs-sck-delay: 23 fsl,spi-sck-cs-delay:
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| /Documentation/ABI/testing/ |
| D | sysfs-kernel-slab | 4 Contact: Pekka Enberg <penberg@cs.helsinki.fi>, 16 Contact: Pekka Enberg <penberg@cs.helsinki.fi>, 25 Contact: Pekka Enberg <penberg@cs.helsinki.fi>, 34 Contact: Pekka Enberg <penberg@cs.helsinki.fi>, 45 Contact: Pekka Enberg <penberg@cs.helsinki.fi>, 56 Contact: Pekka Enberg <penberg@cs.helsinki.fi>, 68 Contact: Pekka Enberg <penberg@cs.helsinki.fi>, 79 Contact: Pekka Enberg <penberg@cs.helsinki.fi>, 90 Contact: Pekka Enberg <penberg@cs.helsinki.fi>, 102 Contact: Pekka Enberg <penberg@cs.helsinki.fi>, [all …]
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| /Documentation/devicetree/bindings/memory-controllers/fsl/ |
| D | fsl,imx-weim.yaml | 59 fsl,weim-cs-gpr: 63 WEIM CS GPR register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0] 65 the CS space configuration. 96 - fsl,weim-cs-timing 117 fsl,weim-cs-gpr: false 135 fsl,weim-cs-timing: 151 fsl,weim-cs-timing: 170 fsl,weim-cs-timing: 190 fsl,weim-cs-gpr = <&gpr>; 198 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
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| /Documentation/devicetree/bindings/mtd/ |
| D | nand-controller.yaml | 31 cs-gpios: 59 cs-gpios = <0>, <&gpioA 1>; /* A single native CS is available */ 64 reg = <0>; /* Native CS */ 69 reg = <1>; /* GPIO CS */
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| /Documentation/scsi/ |
| D | NinjaSCSI.rst | 17 :pcmcia-cs: 3.1.27 29 If you installed pcmcia-cs already, pcmcia reports your card as UNKNOWN 33 You can also use "cardctl" program (this program is in pcmcia-cs source 63 (c) If you use this driver with Kernel 2.2, unpack pcmcia-cs in some directory 64 and make & install. This driver requires the pcmcia-cs header file. 69 $ tar zxvf cs-pcmcia-cs-3.x.x.tar.gz 84 If you use pcmcia-cs-3.1.8 or later, we can use "nsp_cs.conf" file. 119 (f) Start (or restart) pcmcia-cs::
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| /Documentation/iio/ |
| D | ad4000.rst | 35 CS mode, 3-wire turbo mode 39 for these devices, comprises of connecting the controller CS line to device CNV 41 "CS Mode, 3-Wire Turbo Mode" connection in datasheets. 54 | +-------------------| CS | 65 CS mode, 3-wire, without busy indicator 79 +--------------------| CS | 91 the previous wiring configuration but saves the use of a CS line. 107 CS mode, 4-wire without busy indicator 110 In datasheet "4-wire" mode, the controller CS line is connected to the ADC SDI 114 Set ``adi,sdi-pin`` to ``"cs"`` to select this mode. [all …]
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| /Documentation/devicetree/bindings/display/samsung/ |
| D | samsung,exynos7-decon.yaml | 42 cs-setup: 52 Clock cycles for the active period of CS is enabled. 58 Clock cycles for the active period of CS is disabled until write 65 Clock cycles for the active period of CS signal is enabled until
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| /Documentation/devicetree/bindings/mips/cavium/ |
| D | bootbus.txt | 29 - cavium,cs-index: A single cell indicating the chip select that 85 cavium,cs-config@0 { 87 cavium,cs-index = <0>; 105 cavium,cs-config@6 { 107 cavium,cs-index = <6>;
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | adi,ad7944.yaml | 49 CS on the SPI controller. 58 can be connected to the CS line of the SPI controller or to a GPIO, in 59 which case the CS line of the controller is unused. 65 together. The CS line of the SPI controller can be used as the CNV line 103 the conversions and selects the SPI mode of the device (chain or CS). In 105 CS line of the SPI controller.
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