Searched full:cs2 (Results 1 – 18 of 18) sorted by relevance
| /Documentation/ABI/testing/ |
| D | sysfs-bus-iio-sx9324 | 6 SX9324 has 3 inputs, CS0, CS1 and CS2. Hardware layout
19 while CS1 and CS2 are used as shields.
21 [PH1], CS1 is measured, CS0 and CS2 are shield:
23 [PH2], CS2 is measured, CS0 and CS1 are shield:
25 [PH3], CS1 and CS2 are measured (combo mode):
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | marvell,armada-375-pinctrl.txt | 21 mpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2)
51 mpp35 35 gpio, ge1(rxctl), spi1(cs1), spi0(cs2)
58 mpp42 42 gpio, spi1(cs2), led(c0)
61 mpp45 45 gpio, spi0(cs2), pcie0(rstout)
77 mpp61 61 gpio, i2c1(sda), uart1(rxd), spi1(cs2), led(p0)
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| D | marvell,armada-370-pinctrl.txt | 34 spi0(cs2)
77 mpp53 53 gpio, dev(ad14), sd0(clk), tdm(pclk), spi0(cs2),
82 mpp56 56 gpio, dev(cs2), uart1(cts), uart0(cts), spi0(cs3),
96 mpp65 65 gpio, spi0(mosi), spi0(cs2)
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| D | marvell,armada-38x-pinctrl.txt | 31 mpp13 13 gpio, ge0(rxd1), pcie0(clkreq), pcie1(clkreq) [1], spi0(cs2), dev(ad15), pci…
44 mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1)
45 mpp27 27 gpio, spi0(cs3), ge1(txclkout), i2c1(sda), sd0(d7), dev(cs2)
61 mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), n…
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| D | marvell,armada-39x-pinctrl.txt | 45 mpp26 26 gpio, spi0(cs2), i2c1(sck), sd0(d6), dev(cs1)
46 mpp27 27 gpio, spi0(cs3), i2c1(sda), sd0(d7), dev(cs2), ge(txclkout)
62 mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1)
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| D | marvell,armada-xp-pinctrl.txt | 63 mpp41 41 gpio, spi0(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
64 pcie(clkreq1), spi1(cs2)
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| /Documentation/devicetree/bindings/pci/ |
| D | snps,dw-pcie-ep.yaml | 46 CDM/ELBI = 0 and CS2 = 0 or is a contiguous memory region
53 by setting CDM/ELBI = 0 and CS2 = 1. This is an intermix of
63 can be selected by setting CDM/ELBI = 1 and CS2 = 0 wires or can
71 and CS2 = 1. For IP-core releases prior v4.80a, these registers
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| D | snps,dw-pcie.yaml | 55 CDM/ELBI = 0 and CS2 = 0 or is a contiguous memory region
62 by setting CDM/ELBI = 0 and CS2 = 1. This is an intermix of
72 can be selected by setting CDM/ELBI = 1 and CS2 = 0 wires or can
80 and CS2 = 1. For IP-core releases prior v4.80a, these registers
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| D | ti-pci.txt | 49 they are locally accessed within the DIF CS2 space
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| D | snps,dw-pcie-common.yaml | 28 CDM/ELBI (dbi_cs) and CS2 (dbi_cs2) signals (selector bits). Such
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| /Documentation/devicetree/bindings/iio/proximity/ |
| D | semtech,sx9310.yaml | 57 1 2 - CS1 + CS2 (default)
58 0 1 2 3 - CS0 + CS1 + CS2 + CS3
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| D | semtech,sx9324.yaml | 51 For instance, CS0 measured, CS1 shield and CS2 ground is [1, 2, 3]
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| /Documentation/devicetree/bindings/bus/ |
| D | qcom,ebi2.yaml | 25 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
33 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
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| /Documentation/devicetree/bindings/mfd/ |
| D | syscon.yaml | 63 - freecom,fsg-cs2-system-controller
160 - freecom,fsg-cs2-system-controller
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-orion.txt | 52 <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */
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| D | spi-controller.yaml | 42 cs2 : &gpio1 1 0
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| /Documentation/devicetree/bindings/memory-controllers/fsl/ |
| D | fsl,imx-weim.yaml | 67 IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | ti-aemif.txt | 157 nand:cs2 {
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