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/Documentation/admin-guide/media/
Dimx7.rst14 - CMOS Sensor Interface (CSI)
16 - MIPI CSI-2 Receiver
20 MIPI Camera Input ---> MIPI CSI-2 --- > |\
24 | U | ------> CSI ---> Capture
39 This is the MIPI CSI-2 receiver entity. It has one sink pad to receive the pixel
40 data from MIPI CSI-2 camera sensor. It has one source pad, corresponding to the
44 csi-mux
48 sensor with a parallel interface or from MIPI CSI-2 virtual channel 0. It has
49 a single source pad that routes to the CSI.
51 csi chapter
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Dimx.rst16 - Camera Serial Interface (CSI)
31 The CSI is the backend capture unit that interfaces directly with
32 camera sensors over Parallel, BT.656/1120, and MIPI CSI-2 buses.
66 - MIPI CSI-2 Receiver for camera sensors with the MIPI CSI-2 bus
69 to send to a CSI.
84 - Supports parallel, BT.565, and MIPI CSI-2 interfaces.
98 CSI. There is also support in the future for sending frames to the
112 The i.MX5/6 topologies can differ upstream from the IPUv3 CSI video
115 MIPI CSI-2 OV5640 sensor, requires the i.MX6 MIPI CSI-2 receiver. But
117 therefore does not require the MIPI CSI-2 receiver, so it is missing in
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/Documentation/devicetree/bindings/misc/
Difm-csi.txt4 - compatible: "ifm,o2d-csi"
10 - ifm,csi-clk-handle: the phandle to a node in the DT describing the sensor
12 - ifm,csi-addr-bus-width: address bus width (valid values are 16, 24, 25)
13 - ifm,csi-data-bus-width: data bus width (valid values are 8 and 16)
14 - ifm,csi-wait-cycles: sensor bus wait cycles
17 - ifm,csi-byte-swap: if this property is present, the byte swapping on
22 csi@3,0 {
23 compatible = "ifm,o2d-csi";
27 ifm,csi-clk-handle = <&timer7>;
32 ifm,csi-addr-bus-width = <24>;
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/Documentation/devicetree/bindings/soc/imx/
Dfsl,imx8mm-disp-blk-ctrl.yaml14 the NoC and ensuring proper power sequencing of the display and MIPI CSI
36 - const: csi-bridge
39 - const: mipi-csi
47 - const: csi-bridge-axi
48 - const: csi-bridge-apb
49 - const: csi-bridge-core
55 - const: csi-aclk
56 - const: csi-pclk
78 power-domain-names = "bus", "csi-bridge", "lcdif",
79 "mipi-dsi", "mipi-csi";
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Dfsl,imx8mn-disp-blk-ctrl.yaml14 the NoC and ensuring proper power sequencing of the display and MIPI CSI
39 - const: mipi-csi
56 - const: csi-aclk
57 - const: csi-pclk
81 "mipi-csi";
95 "dsi-ref", "csi-aclk", "csi-pclk";
/Documentation/devicetree/bindings/media/
Dnxp,imx7-csi.yaml4 $id: http://devicetree.org/schemas/media/nxp,imx7-csi.yaml#
7 title: i.MX7 and i.MX8 CSI bridge (CMOS Sensor Interface)
13 This is device node for the CMOS Sensor Interface (CSI) which enables the
20 - fsl,imx8mq-csi
21 - fsl,imx7-csi
22 - fsl,imx6ul-csi
24 - const: fsl,imx8mm-csi
25 - const: fsl,imx7-csi
62 - fsl,imx8mm-csi
73 csi: csi@30710000 {
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Dallwinner,sun6i-a31-csi.yaml4 $id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-csi.yaml#
7 title: Allwinner A31 CMOS Sensor Interface (CSI)
16 - allwinner,sun6i-a31-csi
17 - allwinner,sun8i-a83t-csi
18 - allwinner,sun8i-h3-csi
19 - allwinner,sun8i-v3s-csi
20 - allwinner,sun50i-a64-csi
74 description: MIPI CSI-2 bridge input port
108 csi1: csi@1cb4000 {
109 compatible = "allwinner,sun8i-v3s-csi";
Dallwinner,sun4i-a10-csi.yaml4 $id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-csi.yaml#
7 title: Allwinner A10 CMOS Sensor Interface (CSI)
38 - description: The CSI interface clock
39 - description: The CSI DRAM clock
42 - description: The CSI interface clock
43 - description: The CSI ISP clock
44 - description: The CSI DRAM clock
109 csi0: csi@1c09000 {
Dti,omap3isp.txt14 CSI PHYs and receivers registers.
17 syscon : the phandle and register offset to the Complex I/O or CSI-PHY
42 vdd-csiphy1-supply : voltage supply of the CSI-2 PHY 1
43 vdd-csiphy2-supply : voltage supply of the CSI-2 PHY 2
48 lane-polarities : lane polarity (required on CSI-2)
51 be either 1 or 2. (required on CSI-2)
52 clock-lanes : the clock lane (from 1 to 3). (required on CSI-2)
Drenesas,rzg2l-csi2.yaml8 title: Renesas RZ/G2L (and alike SoC's) MIPI CSI-2 receiver
14 The CSI-2 receiver device provides MIPI CSI-2 capabilities for the Renesas RZ/G2L
15 (and alike SoCs). MIPI CSI-2 is part of the CRU block which is used in conjunction
66 Input port node, single endpoint describing the CSI-2 transmitter.
87 Output port node, Image Processing block connected to the CSI-2 receiver.
111 csi: csi@10830400 {
Dimx.txt27 This is the device node for the MIPI CSI-2 Receiver core in the i.MX
28 SoC. This is a Synopsys Designware MIPI CSI-2 host controller core
39 - clocks : the MIPI CSI-2 receiver requires three clocks: hsi_tx
46 connecting with a MIPI CSI-2 source, and ports 1
49 MIPI CSI-2 virtual channel outputs.
Dallwinner,sun8i-a83t-mipi-csi2.yaml7 title: Allwinner A83T MIPI CSI-2
27 - description: Misc CSI Clock
45 description: Input port, connect to a MIPI CSI-2 sensor
67 description: Output port, connect to a CSI controller
90 mipi_csi2: csi@1cb1000 {
Dcdns,csi2tx.txt4 The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
5 4 CSI lanes in output, and up to 4 different pixel streams in input.
30 0 CSI-2 output
43 csi2tx: csi-bridge@0d0e1000 {
/Documentation/devicetree/bindings/media/xilinx/
Dxlnx,csi2rxss.yaml7 title: Xilinx MIPI CSI-2 Receiver Subsystem
13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
17 data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the
20 For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
21 Please note that this bindings includes only the MIPI CSI-2 Rx controller
47 xlnx,csi-pxl-format:
49 This denotes the CSI Data type selected in hw design.
79 xlnx,en-csi-v2-0:
81 description: Present if CSI v2 is enabled in IP configuration.
107 CSI-2 transmitter.
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/Documentation/devicetree/bindings/phy/
Drockchip-inno-csi-dphy.yaml4 $id: http://devicetree.org/schemas/phy/rockchip-inno-csi-dphy.yaml#
13 The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP which
14 connects to the ISP1 (Image Signal Processing unit v1.0) for CSI cameras.
19 - rockchip,px30-csi-dphy
20 - rockchip,rk1808-csi-dphy
21 - rockchip,rk3326-csi-dphy
22 - rockchip,rk3368-csi-dphy
23 - rockchip,rk3568-csi-dphy
71 compatible = "rockchip,px30-csi-dphy";
Dmediatek,mt8365-csi-rx.yaml5 $id: http://devicetree.org/schemas/phy/mediatek,mt8365-csi-rx.yaml#
8 title: Mediatek Sensor Interface MIPI CSI CD-PHY
15 The SENINF CD-PHY is a set of CD-PHY connected to the SENINF CSI-2
23 - mediatek,mt8365-csi-rx
65 compatible = "mediatek,mt8365-csi-rx";
72 compatible = "mediatek,mt8365-csi-rx";
/Documentation/devicetree/bindings/spi/
Drenesas,rzv2m-csi.yaml4 $id: http://devicetree.org/schemas/spi/renesas,rzv2m-csi.yaml#
7 title: Renesas RZ/V2M Clocked Serial Interface (CSI)
18 const: renesas,rzv2m-csi
42 renesas,csi-no-ss:
45 The CSI Slave Selection (SS) pin won't be used to enable transmission and
60 renesas,csi-no-ss: [ spi-slave ]
69 compatible = "renesas,rzv2m-csi";
/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra210-csi.yaml4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra210-csi.yaml#
7 title: NVIDIA Tegra CSI controller
15 pattern: "^csi@[0-9a-f]+$"
19 - nvidia,tegra210-csi
34 - const: csi
/Documentation/driver-api/media/drivers/
Dipu6.rst155 IPU6 input system consists of MIPI D-PHY and several CSI-2 receivers. It can
156 capture image pixel data from camera sensors or other MIPI CSI-2 output devices.
158 D-PHYs and CSI-2 ports lane mapping
164 adaptional layer between D-PHY and CSI-2 receiver controller which includes port
170 there are 12 data lanes and 8 clock lanes, IPU6 support maximum 8 CSI-2 ports,
173 maximum 4 CSI-2 ports. For Meteor Lake, D-PHY has 12 data lanes and 6 clock
174 lanes so IPU6 support maximum 6 CSI-2 ports.
176 .. Note:: Each pair of CSI-2 two ports is a single unit that can share the data
177 lanes. For example, for CSI-2 port 0 and 1, CSI-2 port 0 support
178 maximum 4 data lanes, CSI-2 port 1 support maximum 2 data lanes, CSI-2
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/Documentation/devicetree/bindings/media/i2c/
Dtoshiba,tc358746.yaml13 The Toshiba TC358746 converts a parallel video stream into a MIPI CSI-2
14 stream. The direction can be either parallel-in -> csi-out or csi-in ->
16 interface is only supported in parallel-in -> csi-out mode.
19 parallel-in -> csi-out path.
59 description: MIPI CSI phy voltage supply, 1.2 volts
137 csi-bridge@e {
Dst,st-mipid02.yaml7 title: STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
14 MIPID02 has two CSI-2 input ports, only one of those ports can be
17 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2
56 description: CSI-2 first input port
82 description: CSI-2 second input port
Dtc358743.txt4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
20 MIPI CSI-2 clock is continuous or non-continuous.
25 For further information on the MIPI CSI-2 endpoint node properties, see
/Documentation/devicetree/bindings/display/bridge/
Drenesas,dsi-csi2-tx.yaml7 title: Renesas R-Car MIPI DSI/CSI-2 Encoder
13 This binding describes the MIPI DSI/CSI-2 encoder embedded in the Renesas
14 R-Car Gen4 SoCs. The encoder can operate in either DSI or CSI-2 mode, with up
29 - description: DSI (and CSI-2) functional clock
55 description: DSI/CSI-2 output port
/Documentation/userspace-api/media/v4l/
Dmetafmt-generic.rst23 is used on CSI-2 for 8 bits per :term:`Data Unit`.
57 format is typically used by CSI-2 receivers with a source that transmits
58 MEDIA_BUS_FMT_META_10 and the CSI-2 receiver writes the received data to memory
61 The packing of the data follows the MIPI CSI-2 specification and the padding of
101 is typically used by CSI-2 receivers with a source that transmits
102 MEDIA_BUS_FMT_META_12 and the CSI-2 receiver writes the received data to memory
105 The packing of the data follows the MIPI CSI-2 specification and the padding of
147 format is typically used by CSI-2 receivers with a source that transmits
148 MEDIA_BUS_FMT_META_14 and the CSI-2 receiver writes the received data to memory
151 The packing of the data follows the MIPI CSI-2 specification and the padding of
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/Documentation/driver-api/media/
Dtx-rx.rst10 CSI-2 receiver in an SoC.
17 MIPI CSI-2
20 CSI-2 is a data bus intended for transferring images from cameras to
59 CSI-2 transmitter drivers
79 - Number of data lanes used on the CSI-2 link. This can
97 As part of transitioning to high speed mode, a CSI-2 transmitter typically
119 In the context of CSI-2, the ``.pre_streamon()`` callback is used to transition

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