Searched full:csr (Results 1 – 25 of 51) sorted by relevance
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| /Documentation/devicetree/bindings/clock/ |
| D | xgene.txt | 36 - reg : shall be a list of address and length pairs describing the CSR
40 may include "csr-reg" and/or "div-reg". If this property
42 only "csr-reg".
49 - csr-offset : Offset to the CSR reset register from the reset address base.
51 - csr-mask : CSR reset mask bit. Default is 0xF.
54 - enable-mask : CSR enable mask bit. Default is 0xF.
55 - divider-offset : Offset to the divider CSR register from the divider base.
96 reg-name = "csr-reg";
120 reg-names = "csr-reg", "div-reg";
121 csr-offset = <0x0>;
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| D | nxp,imx95-blk-ctl.yaml | 16 - nxp,imx95-lvds-csr
17 - nxp,imx95-display-csr
18 - nxp,imx95-camera-csr
20 - nxp,imx95-vpu-csr
51 compatible = "nxp,imx95-vpu-csr", "syscon";
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| D | nxp,imx95-display-master-csr.yaml | 4 $id: http://devicetree.org/schemas/clock/nxp,imx95-display-master-csr.yaml#
15 - const: nxp,imx95-display-master-csr
51 compatible = "nxp,imx95-display-master-csr", "syscon";
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| /Documentation/devicetree/bindings/gnss/ |
| D | sirfstar.yaml | 16 by CSR (Cambridge Silicon Radio) and in 2012 the CSR GPS business was
17 acquired by Samsung, while some products remained with CSR. In 2014 CSR
29 - csr,gsd4t
30 - csr,csrg05ta03-icje-r
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| /Documentation/devicetree/bindings/mfd/ |
| D | fsl,imx8qxp-csr.yaml | 4 $id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml#
14 Registers(CSR) module represents a set of miscellaneous registers of a
19 should consider all subnodes of the CSR module as separate child devices.
28 - fsl,imx8qxp-mipi-lvds-csr
29 - fsl,imx8qm-lvds-csr
45 description: The possible child devices of the CSR module.
58 const: fsl,imx8qxp-mipi-lvds-csr
68 const: fsl,imx8qm-lvds-csr
81 compatible = "fsl,imx8qxp-mipi-lvds-csr", "syscon", "simple-mfd";
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| D | brcm,bcm59056.txt | 22 csr, iosr1, iosr2, msr, sdsr1, sdsr2, vsr,
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| /Documentation/devicetree/bindings/net/ |
| D | ipq806x-dwmac.txt | 15 - qcom,qsgmii-csr: should contain a phandle to a syscon device mapping the
16 qsgmii-csr registers.
28 qcom,qsgmii-csr = <&qsgmii_csr>;
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| D | mscc,miim.yaml | 45 Bus (CSR) including VRAP slave.
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| /Documentation/devicetree/bindings/pci/ |
| D | altr,msi-controller.yaml | 20 - description: CSR registers
25 - const: csr
60 reg-names = "csr", "vector_slave";
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| D | xgene-pci.txt | 10 "csr": controller configuration registers.
37 reg-names = "csr", "cfg";
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| D | snps,dw-pcie.yaml | 105 Vendor-specific CSR names. Consider using the generic names above
108 - description: See native 'elbi/app' CSR region for details.
110 - description: See native 'atu' CSR region for details.
112 - description: Syscon-related CSR regions.
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| D | snps,dw-pcie-ep.yaml | 99 Vendor-specific CSR names. Consider using the generic names above
102 - description: See native 'elbi/app' CSR region for details.
104 - description: See native 'atu' CSR region for details.
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| D | snps,dw-pcie-common.yaml | 22 DWC PCIe CSR space is normally accessed over the dedicated Data Bus
155 - description: Controller Non-sticky CSR flags reset
157 - description: Controller sticky CSR flags reset
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| /Documentation/devicetree/bindings/net/pcs/ |
| D | snps,dw-xpcs.yaml | 54 to the multiple 256 register sets. There is a special viewport CSR
56 the CSR address MMD+REG[20:8] is supposed to be written in there
66 each Clause 45 CSR is of 16-bits wide the access instructions must be
97 - const: csr
121 clock-names = "csr", "core", "pad";
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| /Documentation/devicetree/bindings/dma/ |
| D | altr,msgdma.yaml | 32 - const: csr
60 reg-names = "csr", "desc", "resp";
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| D | apm-xgene-dma.txt | 29 reg-names = "csr-reg";
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| /Documentation/devicetree/bindings/phy/ |
| D | airoha,en7581-pcie-phy.yaml | 30 - const: csr-2l
65 reg-names = "csr-2l", "pma0", "pma1",
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| D | fsl,imx8qm-lvds-phy.yaml | 24 by Control and Status Registers(CSR) module in the SoC. The CSR
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| D | fsl,imx8qm-hsio.yaml | 20 - description: HSIO control and status registers(CSR) of the PHY
21 - description: HSIO CSR of the controller bound to the PHY
22 - description: HSIO CSR for MISC
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | fsl,imx8qxp-pxl2dpi.yaml | 19 The i.MX8qxp PXL2DPI is controlled by Control and Status Registers(CSR) module.
20 The CSR module, as a system controller, contains the PXL2DPI's configuration
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| D | fsl,imx8qxp-ldb.yaml | 15 The i.MX8qm/qxp LDB is controlled by Control and Status Registers(CSR) module.
16 The CSR module, as a system controller, contains the LDB's configuration
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| /Documentation/devicetree/bindings/soc/litex/ |
| D | litex,soc-controller.yaml | 12 Its purpose is to verify LiteX CSR (Control&Status Register) access
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| /Documentation/devicetree/bindings/timer/ |
| D | riscv,timer.yaml | 14 based on the time CSR defined by the RISC-V privileged specification. The
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | pinctrl-sirf.txt | 1 CSR SiRFprimaII pinmux controller
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| /Documentation/devicetree/bindings/misc/ |
| D | idt,89hpesx.yaml | 7 title: EEPROM / CSR SMBus-slave interface of IDT 89HPESx devices
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