Searched full:csrs (Results 1 – 14 of 14) sorted by relevance
| /Documentation/devicetree/bindings/net/pcs/ |
| D | snps,dw-xpcs.yaml | 21 The PCS CSRs can be accessible either over the Ethernet MDIO bus or directly
49 of the MDIO bus device. If DW XPCS CSRs space is accessed over the
57 so the corresponding subset would be mapped to the lowest 255 CSRs.
65 The way the CSRs are mapped to the memory is platform depended. Since
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.yaml | 10 RISC-V cores include Control Status Registers (CSRs) which are local to
12 software. Some of these CSRs are used to control local interrupts connected
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| D | riscv,imsics.yaml | 19 a IMSIC interrupt file is done using AIA CSRs and it also has a 4KB MMIO
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| /Documentation/devicetree/bindings/pci/ |
| D | snps,dw-pcie-ep.yaml | 47 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
73 set of viewport CSRs mapped into the PL space. Note iATU is
79 CSRs mapped in a non-standard base address. The registers offset
86 PCS and PHY CSRs accessible over a dedicated memory mapped
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| D | snps,dw-pcie.yaml | 56 with all spaces. Note iATU/eDMA CSRs are indirectly accessible
82 set of viewport CSRs mapped into the PL space. Note iATU is
88 CSRs mapped in a non-standard base address. The registers offset
95 PCS and PHY CSRs accessible over a dedicated memory mapped
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| D | snps,dw-pcie-common.yaml | 79 basically the set of the controller CSRs.
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| /Documentation/devicetree/bindings/soc/litex/ |
| D | litex,soc-controller.yaml | 13 operations and provide functions for other drivers to read/write CSRs
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | snps,dw-umctl2-ddrc.yaml | 60 A standard set of the clock sources contains CSRs bus clock, AXI-ports
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| /Documentation/networking/device_drivers/ethernet/intel/ |
| D | iavf.rst | 99 - 4 Queue Pairs (QP) and associated Configuration Status Registers (CSRs)
103 - 1 control queue, with i40e descriptors, CSRs and ring format
104 - 5 MSI-X interrupt vectors and corresponding i40e CSRs
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| /Documentation/arch/loongarch/ |
| D | introduction.rst | 18 registers (FPRs), vector registers (VRs) and control status registers (CSRs)
93 CSRs section in Registers
96 CSRs can only be accessed from privileged mode (PLV0):
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| /Documentation/devicetree/bindings/riscv/ |
| D | extensions.yaml | 133 The standard Smstateen extension for controlling access to CSRs
390 special case read-only CSRs, that were moved into the Zicntr and
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| /Documentation/translations/zh_CN/arch/loongarch/ |
| D | introduction.rst | 22 和用于特权模式（PLV0）的控制状态寄存器（CSRs）。
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| /Documentation/translations/zh_TW/arch/loongarch/ |
| D | introduction.rst | 22 和用於特權模式（PLV0）的控制狀態寄存器（CSRs）。
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| /Documentation/admin-guide/sysctl/ |
| D | kernel.rst | 1039 and insret CSRs only). Note that this legacy value is deprecated and will be
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