Searched full:calxeda (Results 1 – 10 of 10) sorted by relevance
| /Documentation/devicetree/bindings/ata/ |
| D | sata_highbank.yaml | 7 title: Calxeda AHCI SATA Controller
10 The Calxeda SATA controller mostly conforms to the AHCI interface
19 const: calxeda,hb-ahci
29 calxeda,pre-clocks:
35 calxeda,post-clocks:
41 calxeda,led-order:
47 calxeda,port-phys:
57 calxeda,tx-atten:
65 calxeda,sgpio-gpio:
82 compatible = "calxeda,hb-ahci";
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| /Documentation/devicetree/bindings/clock/ |
| D | calxeda.yaml | 4 $id: http://devicetree.org/schemas/clock/calxeda.yaml#
7 title: Calxeda highbank platform Clock Controller
10 This binding covers the Calxeda SoC internal peripheral and bus clocks
24 - calxeda,hb-pll-clock
25 - calxeda,hb-a9periph-clock
26 - calxeda,hb-a9bus-clock
27 - calxeda,hb-emmc-clock
46 compatible = "calxeda,hb-sregs";
61 compatible = "calxeda,hb-pll-clock";
68 compatible = "calxeda,hb-pll-clock";
[all …]
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | calxeda-ddr-ctrlr.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/calxeda-ddr-ctrlr.yaml#
7 title: Calxeda DDR memory controller
10 The Calxeda DDR memory controller is initialised and programmed by the
20 - calxeda,hb-ddr-ctrl
21 - calxeda,ecx-2000-ddr-ctrl
39 compatible = "calxeda,hb-ddr-ctrl";
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| /Documentation/devicetree/bindings/arm/ |
| D | calxeda.yaml | 4 $id: http://devicetree.org/schemas/arm/calxeda.yaml#
7 title: Calxeda Platforms
12 Bindings for boards with Calxeda Cortex-A9 based ECX-1000 (Highbank) SOC
21 - calxeda,highbank
22 - calxeda,ecx-2000
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| /Documentation/devicetree/bindings/arm/calxeda/ |
| D | l2ecc.yaml | 4 $id: http://devicetree.org/schemas/arm/calxeda/l2ecc.yaml#
7 title: Calxeda Highbank L2 cache ECC
10 Binding for the Calxeda Highbank L2 cache controller ECC device.
19 const: calxeda,hb-sregs-l2-ecc
39 compatible = "calxeda,hb-sregs-l2-ecc";
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| D | hb-sregs.yaml | 4 $id: http://devicetree.org/schemas/arm/calxeda/hb-sregs.yaml#
7 title: Calxeda Highbank system registers
10 The Calxeda Highbank system has a block of MMIO registers controlling
19 const: calxeda,hb-sregs
36 compatible = "calxeda,hb-sregs";
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| /Documentation/devicetree/bindings/phy/ |
| D | calxeda-combophy.yaml | 4 $id: http://devicetree.org/schemas/phy/calxeda-combophy.yaml#
7 title: Calxeda Highbank Combination PHYs for SATA
10 The Calxeda Combination PHYs connect the SoC to the internal fabric
22 const: calxeda,hb-combophy
46 compatible = "calxeda,hb-combophy";
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| /Documentation/devicetree/bindings/net/ |
| D | calxeda-xgmac.yaml | 4 $id: http://devicetree.org/schemas/net/calxeda-xgmac.yaml#
7 title: Calxeda Highbank 10Gb XGMAC Ethernet controller
10 The Calxeda XGMAC Ethernet controllers are directly connected to the
21 const: calxeda,hb-xgmac
46 compatible = "calxeda,hb-xgmac";
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| /Documentation/devicetree/bindings/iommu/ |
| D | arm,smmu.yaml | 203 calxeda,smmu-secure-config-access:
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| /Documentation/devicetree/bindings/ |
| D | vendor-prefixes.yaml | 247 "^calxeda,.*":
248 description: Calxeda
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