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/Documentation/devicetree/bindings/spi/
Dsprd,spi-adi.yaml20 ADI controller has 50 channels including 2 software read/write channels and
21 48 hardware channels to access analog chip. For 2 software read/write channels,
22 users should set ADI registers to access analog chip. For hardware channels,
26 triggered by hardware components instead of ADI software channels.
28 Thus we introduce one property named "sprd,hw-channels" to configure hardware
29 channels, the first value specifies the hardware channel id which is used to
34 one system is reading/writing data by ADI software channels, that should be under
36 data by ADI software channels at the same time, or two parallel routine of setting
40 The new version ADI controller supplies multiple master channels for different
64 sprd,hw-channels:
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/Documentation/arch/mips/
Dingenic-tcu.rst8 hardware block. It features up to eight channels, that can be used as
11 - JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
12 have eight channels.
18 - Each one of the TCU channels has its own clock, which can be reparented to three
28 - mode TCU1: channels cannot work in sleep mode, but are easier to
30 - mode TCU2: channels can work in sleep mode, but the operation is a bit
31 more complicated than with TCU1 channels.
35 - On the oldest SoCs (up to JZ4740), all of the eight channels operate in
38 - On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the
41 - Each channel can generate an interrupt. Some channels share an interrupt
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/Documentation/ABI/stable/
Dsysfs-bus-vmbus33 Description: The mapping of which primary/sub channels are bound to which
59 What: /sys/bus/vmbus/devices/<UUID>/channels/<N>
66 What: /sys/bus/vmbus/devices/<UUID>/channels/<N>/cpu
73 What: /sys/bus/vmbus/devices/<UUID>/channels/<N>/in_mask
80 What: /sys/bus/vmbus/devices/<UUID>/channels/<N>/latency
85 performance critical channels (storage, network, etc.) that use
89 What: /sys/bus/vmbus/devices/<UUID>/channels/<N>/out_mask
96 What: /sys/bus/vmbus/devices/<UUID>/channels/<N>/pending
101 performance critical channels (storage, network, etc.) that use
105 What: /sys/bus/vmbus/devices/<UUID>/channels/<N>/read_avail
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/Documentation/trace/coresight/
Dcoresight-ect.rst16 devices via numbered channels, in order to propagate events between devices.
23 0 U 0 out_trigs : : Channels ***** :::::::
31 channels. When an input trigger becomes active, the attached channel will
75 channels ctmid enable nr_trigger_cons mgmt power powered regs
89 * ``channels``: Contains the channel API - CTI main programming interface.
130 Channels API Directory
133 This provides an easy way to attach triggers to channels, without needing
139 >$ ls ./cti_sys0/channels/
155 >$ echo 0 1 > ./cti_sys0/channels/trigout_attach
156 >$ echo 0 > ./cti_sys0/channels/chan_set
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/Documentation/devicetree/bindings/iio/multiplexer/
Dio-channel-mux.yaml16 For each non-empty string in the channels property, an io-channel will be
18 of strings in the channels property, and also matches the mux controller
27 io-channels:
37 channels:
53 - io-channels
56 - channels
73 io-channels = <&adc 0>;
77 channels = "sync", "in", "system-regulator";
/Documentation/ABI/testing/
Dsysfs-bus-coresight-devices-cti137 What: /sys/bus/coresight/devices/<cti-name>/channels/trigin_attach
143 What: /sys/bus/coresight/devices/<cti-name>/channels/trigin_detach
149 What: /sys/bus/coresight/devices/<cti-name>/channels/trigout_attach
155 What: /sys/bus/coresight/devices/<cti-name>/channels/trigout_detach
161 What: /sys/bus/coresight/devices/<cti-name>/channels/chan_gate_enable
166 channels through the gate (R).
168 What: /sys/bus/coresight/devices/<cti-name>/channels/chan_gate_disable
174 What: /sys/bus/coresight/devices/<cti-name>/channels/chan_set
180 What: /sys/bus/coresight/devices/<cti-name>/channels/chan_clear
186 What: /sys/bus/coresight/devices/<cti-name>/channels/chan_pulse
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/Documentation/devicetree/bindings/sound/
Dxlnx,i2s.txt12 - xlnx,num-channels: Number of I2S streams. Can be any of 1, 2, 3, 4.
13 supported channels = 2 * xlnx,num-channels
21 xlnx,num-channels = <1>;
27 xlnx,num-channels = <1>;
Daudio-iio-aux.yaml13 Auxiliary device based on Industrial I/O device channels
22 io-channels:
24 Industrial I/O device channels used
28 Industrial I/O channel names related to io-channels.
51 - io-channels
60 io-channels = <&iio 0>, <&iio 1>, <&iio 2>, <&iio 3>;
Drockchip-i2s.yaml90 rockchip,capture-channels:
94 Max capture channels, if not set, 2 channels default.
96 rockchip,playback-channels:
100 Max playback channels, if not set, 8 channels default.
137 rockchip,capture-channels = <2>;
138 rockchip,playback-channels = <8>;
/Documentation/devicetree/bindings/iio/adc/
Dmaxim,max1027.yaml19 # 10-bit 8 channels
21 # 10-bit 12 channels
23 # 10-bit 16 channels
25 # 12-bit 8 channels
27 # 12-bit 12 channels
29 # 12-bit 16 channels
Dst,stm32-adc.yaml11 It has several multiplexed input channels. Conversions can be performed
292 st,adc-channels:
294 List of single-ended channels muxed for this ADC. It can have up to:
295 - 16 channels, numbered from 0 to 15 (for in0..in15) on stm32f4
296 - 19 channels, numbered from 0 to 18 (for in0..in18) on stm32mp13.
297 - 20 channels, numbered from 0 to 19 (for in0..in19) on stm32h7 and
302 st,adc-diff-channels:
304 List of differential channels muxed for this ADC. Some channels can
309 Note: At least one of "st,adc-channels" or "st,adc-diff-channels" is
312 Both properties can be used together. Some channels can be
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Dadi,ad7124.yaml67 Represents the external channels which are connected to the ADC.
72 The channel number. It can have up to 8 channels on ad7124-4
73 and 16 channels on ad7124-8, numbered from 0 to 15.
89 diff-channels: true
103 - diff-channels
133 diff-channels = <0 1>;
141 diff-channels = <2 3>;
149 diff-channels = <4 5>;
154 diff-channels = <6 7>;
Dadc.yaml7 title: IIO Common Properties for ADC Channels
13 A few properties are defined in a common way ADC channels.
31 diff-channels:
44 When devices combine single-ended and differential channels, allow the
46 differential channels). If this and diff-channels are not present reg
76 - diff-channels
Dti,ads1119.yaml64 diff-channels:
66 Differential input channels AIN0-AIN1, AIN2-AIN3 and AIN1-AIN2.
80 Single-ended input channels AIN0, AIN1, AIN2 and AIN3.
86 - diff-channels
127 diff-channels = <0 1>;
147 diff-channels = <1 2>;
152 diff-channels = <2 3>;
/Documentation/hwmon/
Dina3221.rst32 in[123]_input Bus voltage(mV) channels
33 curr[123]_input Current(mA) measurement channels
34 shunt[123]_resistor Shunt resistance(uOhm) channels
43 in[456]_input Shunt voltage(uV) for channels 1, 2, and 3 respectively
44 in7_input Sum of shunt voltage(uV) channels
46 curr4_input Sum of current(mA) measurement channels,
47 (only available when all channels use the same resistor
52 (only effective when all channels use the same resistor
66 * C: number of enabled channels
/Documentation/devicetree/bindings/dma/
Dowl-dma.yaml11 supporting 10 independent DMA channels for the Actions Semi S700 SoC and 12
12 independent DMA channels for the S500 and S900 SoC variants.
33 DMA channels.
39 dma-channels:
58 - dma-channels
75 dma-channels = <12>;
Dbrcm,bcm2835-dma.yaml13 The BCM2835 DMA controller has 16 channels in total. Only the lower
14 13 channels have an associated IRQ. Some arbitrary channels are used by the
15 VideoCore firmware (1,3,6,7 in the current firmware version). The channels
30 Should contain the DMA interrupts associated to the DMA channels in
46 Bitmask of available DMA channels in ascending order that are
80 /* unused shared irq for all channels */
Ddma-common.yaml29 Bitmask of available DMA channels in ascending order that are
32 The first item in the array is for channels 0-31, the second is for
33 channels 32-63, etc.
40 dma-channels:
43 Number of DMA channels supported by the controller.
Dapple,admac.yaml13 The controller has been seen with up to 24 channels. Even-numbered channels
14 are TX-only, odd-numbered are RX-only. Individual channels are coupled to
40 dma-channels:
67 - dma-channels
85 dma-channels = <24>;
/Documentation/trace/
Dstm.rst11 these masters and channels are statically allocated to certain
24 48 to 63 and channels 0 to 127.
28 identifiers to ranges of masters and channels. If these rules (policy)
33 have a name (string identifier) and a range of masters and channels
41 channels masters
44 $ cat /config/stp-policy/dummy_stm.my-policy/user/channels
48 masters 48 through 63 and channel allocation pool has channels 0
78 contiguous range of master/channels from the beginning of the device's
85 mmu) will usually contain multiple channels' mmios, so the user will
86 need to allocate that many channels to themselves (via the
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/Documentation/driver-api/dmaengine/
Ddmatest.rst16 test multiple channels at the same time, and it can start multiple threads
20 The test suite works only on the channels that have at least one
74 After the channels are specified, each thread is set as pending. All threads
78 A list of available channels can be found by running the following command::
153 Allocating Channels
156 Channels do not need to be configured prior to starting a test run. Attempting
157 to run the test without configuring the channels will result in testing any
158 channels that are available.
163 dmatest: No channels configured, continue with any
165 Channels are registered using the "channel" parameter. Channels can be requested by their
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/Documentation/devicetree/bindings/hwmon/
Diio-hwmon.yaml20 io-channels:
24 List of phandles to ADC channels to read the monitoring values
28 - io-channels
36 io-channels = <&adc 1>, <&adc 2>;
Dti,ina3221.yaml43 description: The node contains optional child nodes for three channels.
44 Each child node describes the information of input source. Input channels
45 default to enabled in the chip. Unless channels are explicitly disabled
46 in device-tree, input channels will be enabled.
65 shunt-voltage conversions for the desired channels in order to
74 to use the same shunt-resistor value on all enabled channels. If
77 exclude specific channels from the summation control function.
104 * Input channels are enabled by default in the device and so
/Documentation/devicetree/bindings/soc/qcom/
Dqcom,apr.yaml59 qcom,glink-channels:
79 qcom,smd-channels:
121 qcom,glink-channels:
127 qcom,glink-channels:
133 - qcom,glink-channels
136 qcom,smd-channels: false
140 - qcom,smd-channels
143 qcom,glink-channels: false
153 qcom,glink-channels = "apr_audio_svc";
190 qcom,glink-channels = "adsp_apps";
/Documentation/devicetree/bindings/dma/xilinx/
Dxilinx_dma.txt2 It can be configured to have one channel or two channels. If configured
3 as two channels, one is to transmit to the video device and another is
7 target devices. It can be configured to have one channel or two channels.
8 If configured as two channels, one is to transmit to the device and another
16 and receive channels.
29 two channels per device. This node specifies the properties of each
61 {1}, flush both channels
85 - dma-channels: Number of dma channels in child node.
121 from '16' and is in [16-31] range. These channels ID are

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